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| R8A66597FP/DFP/BG ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller) REJ03F0229-0101 Rev1.01 Oct 17, 2008 1 Overview 1.1 Overview The R8A66597 is a Universal Serial Bus (USB) Controller equipped with USB Host functions and Peripheral functions applicable for On-The-Go. When selecting the Host Controller function, it has two USB ports available for Hi-Speed, Full-Speed, and Low-Speed transfer compliant with USB Specification Revision 2.0. When selecting the Peripheral Controller function, it has one USB port available for Hi-Speed and Full-Speed transfer compliant with USB Specification Revision 2.0. This controller has a built-in USB transceiver and is compatible with all the transfer types defined in USB Specification Revision 2.0. The internal buffer memory is 8.5K, and a maximum ten pipes can be used for transferring data. For Pipe1 to Pipe9, any endpoint address can be assigned matching the peripheral functions for communication or user system. Separate bus or multiplex bus can be selected for the CPU connection. A split bus interface (exclusively for the DMA interface) that is different from the CPU bus interface is provided and is suitable for systems demanding high-performance data transfer. 1.2 Features 1.2.1 * * * Built-in Host Controller and Peripheral Controller compatible with Hi-Speed USB Built-in USB Host Controller and Peripheral Controller Toggle between USB Host functions and Peripheral functions is possible according to what is written to the register Built-in USB transceiver 1.2.2 * * * * Low power consumption 1.5V core power consumes less power when operating With the installed Low Power Sleep Mode functions, less power is consumed when the USB is not in use, which is also applicable for portable devices Standby power consumption can be greatly reduced by keeping only the VIF power source ON when not using the USB function. Operational with a 3.3V single power supply using the internal 1.5V core power regulator 1.2.3 * Space-saving package Few external devices and space-saving package VBUS signal can be connected directly to the controller input pin Built-in D+ pull-up resistor (for Peripheral function) Built-in D+ and D- pull-down resistors (for Host function) Built-in D+ and D- terminating resistors (for Hi-Speed operations) Built-in D+ and D- output resistors (for Full-Speed and Low-Speed operations) Rev1.01 Oct 17, 2008 page 1 of 183 R8A66597FP/DFP/BG 1.2.4 * Compatible with all USB transfer types Compatible with all USB transfer types, including isochronous transfer Control transfer Bulk transfer Interrupt transfer (not compatible with high-bandwidth) Isochronous transfer (not compatible with high-bandwidth) 1.2.5 * * * * Bus interface 16-bit CPU bus interface Compatible with 16-bit separate bus/16-bit multiplex bus Compatible with DMA transfer in 8-bit/16-bit access (slave function) 8-bit split bus (exclusive for external direct memory access controller (DMAC)) interface Built-in two DMA interface channels DMA transfer provides 40MB/second high-performance data transfer 1.2.6 * * * * * Pipe configuration Built-in 8.5KB buffer memory for USB communication Maximum of ten pipes can be selected (including default control pipe) Programmable pipe configuration Any endpoint address can be assigned to Pipe1 to Pipe9 Transfer conditions that can be written for each pipe Pipe0: Control transfer, single buffer fixed at 256 bytes Pipe1~Pipe2: Bulk transfer/Isochronous transfer, continuous transfer modes. programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable) Pipe3~Pipe5: Bulk transfer, continuous transfer modes, programmable buffer size (specifiable up to 2K bytes per side, double buffer also specifiable) Pipe6~Pipe9: Interrupt transfer, single buffer fixed at 64 bytes 1.2.7 * * * * * Features when selecting Host functions Compatible with Hi-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed transfer (1.5Mbps) Several Peripheral devices can be connected through one tier hub Reset handshake auto response SOF and packet transmission schedule automation Transfer interval setup function for Isochronous and Interrupt transfer 1.2.8 * * * * * * * Features when selecting Peripheral functions Compatible with Hi-Speed (480Mbps) and Full-Speed transfer (12Mbps) Auto identification of Hi-Speed or Full-Speed operations according to reset handshake auto response Control transfer stage management function Device state management function Auto response function related to SET_ADDRESS request NAK response interrupt function (NRDY) SOF interpolation function 1.2.9 * * Functions that Provide On-The-Go Support Built-in ID pin and ID pin monitor bit enables determination of A-Device/B-Device at start-up Built-in control bit facilitates Host Negotiation Protocol 1.2.10 Other functions * * * * * * * * * Rev1.01 Compatible with the CPU of big-endian or little-endian according to the byte-endian swap function Transfer end function according to transaction count End function of DMA transfer by external trigger (DEND pin) SOF plus output function Three types of input clock can be selected by built-in PLL Select from 48MHz/24MHz/12MHz Function to modify the BRDY interrupt event notification timing (BFRE) Function to clear the auto buffer memory after the pipe data specified in the DxFIFO port is read (DCLRM) Function to provide the auto clock from clock stop status NAK setting function (SHTNAK) for PID response corresponding to transfer end Oct 17, 2008 Page 2 of 183 Confidential R8A66597FP/DFP/BG 1.2.11 Usage Navigation systems, DVD recorders, set-top boxes, audio devices, printers, external storage devices and other devices equipped with USB Rev1.01 Oct 17, 2008 Page 3 of 183 Confidential R8A66597FP/DFP/BG 1.3 Package 1.3.1 Pin Layout Figure 1.1 shows the pin layout (top view) for this controller. MPBUS G ND CS_N WR1_N WR0_N RD_N A7/ALE A6 RST_N VCC VDD GND A3 VIF A5 A4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND D0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 VIF GND D8 D9 D10 D11 D12 D13 D14 D15 GND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND VBUS 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2 A1 R8A66597FP/DFP TOP VIEW DP0 DM0 GND DP1 DM1 VCC OVCUR0B OVCUR0A ID0 EXTLP0 VBOUT0 OVCUR1 VBOUT1 REFRIN AGND AVCC XOUT XIN VCC GND DREQ0_N DACK0_N DACK1_N DEND1_N VIF INT_N SO F_N DEND0_N DREQ1_N VDD GND SD0 The "_N" in the signal name indicates that the signal is in the "L" active state. Package R8A66597 : PLQP0080LA-A : 80pinLQFP (0.4mm pitch) Figure 1.1 R8A66597FP/DFP Pin Layout Rev1.01 Oct 17, 2008 Page 4 of 183 Confidential SD7 VIF SD1 SD2 SD3 SD4 SD5 SD6 R8A66597FP/DFP/BG R8A66597BG ( TOP VIEW ) 1 A GND 2 D15 3 D14 4 D10 5 GND 6 D5/AD5 7 D2/AD2 8 D0 9 GND A B VIF INT_N D13 D11 VIF D4/AD4 D1/AD1 CS_N VIF B C DREQ0_N DACK0_N SOF_N D9 D7/AD7 D3/AD3 WR1_N W R0_N RD_N C D DREQ1_N DACK1_N DEND0_N D12 D8 D6/AD6 A6 A4 A5 D E GND VDD DEND1_N SD0 GND A7/ALE A3 VDD GND E F SD2 SD3 SD4 SD1 VBOUT0 A2 GND MPBUS A1 F G SD5 SD6 AVCC VBOUT1 OVCUR1 EXTLP0 ID0 RST_N VCC G H VIF SD7 XIN AGND VCC OVCUR0B OVCUR0A GND VBUS H J GND 1 VCC 2 XOUT 3 REFRIN 4 DM1 5 DP1 6 GND 7 DM0 8 DP0 9 J The "_N" in the signal name indicates that the signal is in the "L" active Package R8A66597BG : PLBG0081KA-A : 81pinLFBGA (0.5mm pitch) Figure 1.2 R8A66597BG Pin Layout Rev1.01 Oct 17, 2008 Page 5 of 183 Confidential R8A66597FP/DFP/BG 1.4 Pin Description Pin descriptions are given in Table 1.1, and the processing method of unused pins is given in Table 1.2. Table 1.1 Pin Description Classification Pin Status *5) Pin Name Name I/O Function Number of Pins Being Immediately After Reset Reset D15-0 AD7-1 A7-1 ALE CPU bus interface CS_N RD_N WR0_N WR1_N MPBUS Data bus Multiplex address bus Address bus Address latch enabled Chip select Read strobe I/O This is a 16-bit data bus. When selecting to the multiplex bus, these pins I/O are used in the time division as a part of the data bus (D7-D1) or address bus (A7-A1). This is the address bus. IN A0 does not exist for the 16-bit data bus. While selecting to the multiplex bus, the A7 pin IN is used as an ALE signal. IN The controller is selected in "L" level. IN 16 *2) Input *3) Input *2) Input *3) Input Input *4) Input Input *4) Input *4) Input *1) Input (Hi-Z) H 7 1 1 1 1 1 8 2 2 Input *4) Input Input *4) Input *4) Input *1) Input (Hi-Z) H SPLIT bus interface SD7-0 DREQ0_N DREQ1_N DACK0_N DACK1_N DMA bus interface DEND0_N DEND1_N Interrupt/ SOF output INT_N SOF_N XIN Clock XOUT System control USB bus interface Reads the data from the register of this controller in "L" level. D7-0 Byte write Writes D7-D0 in the register of this controller at IN strobe the rising edge. D15-8 byte write Writes D15-D8 in the register of this controller IN strobe at the rising edge. This is a separate bus in "L" level. This is a Bus mode IN multiplex bus in "H" Level. Fix either "H" or "L" selection level. When the split bus is selected, it functions as Split data bus I/O the split data bus. Notifies the DMA transfer request of D0FIFO DMA request OUT port and D1FIFO port. DMA Enter the DMA acknowledgement signal of acknowledgeme IN D0FIFO port and D1FIFO port. nt For FIFO port access write direction: Receives transmission completion signal as an input DMA transfer I/O signal from other chips or CPU. end For FIFO port access read direction: Shows the last transmitted data as an output signal. Notifies various types of interrupts related to USB communication by "L" active. Active is by Interrupt OUT default "L" active, however it can be changed to "H" active by modifying the setup value of INTA bit in the software. For Host function: When the controller issues an SOF, outputs an SOF pluse SOF pulse by "L" active. OUT output For Peripheral function: When an SOF is detected, outputs an SOF pulse by "L" active. Input for Connect crystal oscillator between XIN and IN oscillation XOUT. Connect external clock signal to XIN in order to input external clock, and leave open Output for OUT XOUT. oscillation Reset signal IN Resets this controller at "L" level. Input Input 2 Input (Hi-Z) Input (Hi-Z) 1 H H 1 H H 1 1 1 Input (L) Input (H) Rev1.01 Oct 17, 2008 Page 6 of 183 Confidential R8A66597FP/DFP/BG Classification Pin Status *5) Pin Name Name I/O Function Number of Pins Being Immediately After Reset Reset Input (Hi-Z) Input (Hi-Z) USB bus interface DP0 DP1 DM0 DM1 USB D+ data USB D-data I/O Connect to D+ pin of USB bus. I/O Connect to D- pin of USB bus. When Host Controller function is selected: leave open or connect directly to Vbus of USB bus. This pin cannot supply Vbus to the connected IN device. When Peripheral Controller function is selected: Connect directly to Vbus of USB bus. Can detect Vbus connection/disconnection. Connect to 5V when not connecting to Vbus. Connect to analog GND pin through 5.6k1% IN resistor. When using USB Mini-AB receptacle, connect IN to ID pin. Used for ON/OFF output to external power circuit. Connect to external power circuit for OUT Vbus supply. VBOUT1 pin cannot be used when using DP0/DM0 as OTG. Used for input of over-current detection from external power circuit. Connect to PORT0 external power circuit. IN When input for over-current detection from external power circuit is one pin, connect to OVCUR0A and fix OVCUR0B to High or Low. Used for input of over-current detection from external power circuit. Connect to PORT1 IN external power circuit. OVCUR1 pin cannot be used when using DP0/DM0 as OTG. Used for low-power consumption mode ON/OFF switch when external power circuit OUT has low-consumption mode. Connect to PORT0 external power circuit. - Connect to 3.3V. - Connect to 3.3V. Connect to 3.3V or 1.8V. Output 1.5V with internal regulator -generated. For stability core power, Connect the 4.7uF OUT and 0.1uF capacitor between GND. No connection of external power is necessary. - 2 2 Input (Hi-Z) Input (Hi-Z) VBUS monitoring input VBUS VBUS input 1 Input (Hi-Z) Input (Hi-Z) Reference resistance On-The-Go related REFRIN ID0 Reference input ID input 1 1 Input Input VBOUT0 VBOUT1 External power on 2 L L OVCUR0A Power OVCUR0B manageme nt related if USB Host OVCUR1 Overcurrent input for Port0 2 Input Input Overcurrent input for Port1 Control of external power for low power consumption Analog power Analog GND Power GND IO power Core power 1 Input Input EXTLP0 AVCC AGND VCC Power /GND GND VIF VDD 1 1 1 3 9 (FP) 10(BG) 4 2 L L *1) *2) *3) *4) The input level of MPBUS pin must be fixed. Do not switch the level during controller operations. Pin is for OUTPUT when CS N = "L" and RD N="L", otherwise INPUT. Hi-Z input (open) is enabled when MPBUS = "H". Maintain status (a) or (b) as described below during reset and immediately after reset release for CS_N, WR0_N and WR1_N signals. (a) CS_N = "H" (b) WR0 N = "H" and WR1_N = "H" *5) Explanations for "Pin Status" column (a) input: input port, Hi-Z status (open) disabled (b) Input (Hi-Z): input port, Hi-Z status (open) enabled (c) H, L, H/L: indicates output port status Oct 17, 2008 Page 7 of 183 Rev1.01 Confidential R8A66597FP/DFP/BG Table 1.2 Example of Unused R8A66597 Pin Classification Split Bus Interface DMA Bus Interface SOF Ouptput Pin Name SD7-0 DREQ0_N, DREQ1_N DACK0_N, DACK1_N DEND0_N, DEND1_N SOF_N Process Contents Open Open Fixed to VIF "H" level *1) Open *2) Open When using Host Function: open When using Peripheral function: Connect to VBUS signal on USB connector Fixed to "L" Open Fixed to "L" Open VBUS Monitor Input VBUS USB Host: Power Supply Management related ID0 VBOUT0, VBOUT1 OVCUR0A, OVCUR0B, OVCUR1 EXTLP0 *1) *2) When not using DACKn_N pin, set DMAnCFG register DFROM bit to "000" and DACKA bit to "0" (n=0, 1) When not using DENDn_N pin, set DMAnCFG register DENDE bit to "0" (n=0, 1) Rev1.01 Oct 17, 2008 Page 8 of 183 Confidential R8A66597FP/DFP/BG 1.5 Structure of Pin Functions Block diagram of the controller pin functions is shown in Figure 1.3. CPU bus interface D15-8, D7-1(/AD7-1), D0 A7/ALE, A6-1 CS_N RD_N WR0_N WR1_N MPBUS Interrupt/SOFoutput INT_N SOF_N 16 7 Clock XIN XOUT VBUS monitoring input VBUS USB interface 0 DP0, DM0 VBOUT0 EXTLP0 OVCUR0A, OVCUR0B USB interface 1 DP1, DM1 VBOUT1 OVCUR1 On-The-Go related pin ID0 Reference resistance REFRIN R8A66597 DMA interface DREQ0_N DACK0_N DEND0_N DREQ1_N DACK1_N DEND1_N Split bus SD7-0 System control RST_N 2 2 2 8 Figure 1.3 Block Diagram of Pin Functions Rev1.01 Oct 17, 2008 Page 9 of 183 Confidential R8A66597FP/DFP/BG 1.6 Functional Overview 1.6.1 Selection of controller functions The controller can toggle between Host functions and Peripheral functions according to what is written to the register. The hardware can automatically identify the USB transmission speed, irrespective of whether the Host or Peripheral function is selected. 1.6.2 Bus interface The controller is compatible with the bus interfaces given below. 1.6.2.1 External bus interface The CPU accesses the control register of the controller using the CPU bus interface. There are two types of access below for the bus interface from the CPU. Access using a chip select pin (CS_N) and three strobe pins (RD_N, WR0_N and WR1_N). 16-bit separate bus Seven address buses (A7-1) and sixteen data buses (D15-0) are used. 16-bit multiplex bus The ALE pin (ALE) and sixteen data buses (D15-0) are used. The data bus uses the address and data in the time division. Separate bus or multiplex bus are selected at the MPBUS pin signal level while canceling the hardware reset. 1.6.2.2 FIFO buffer memory access method This controller is compatible with the following two access types as an access method of the FIFO buffer memory for USB data transmission. Read (write) of the data from the FIFO buffer memory is possible by accessing (read/write) the FIFO port from the CPU (DMAC). (1) CPU access Write the data in, or read the data from, the FIFO buffer memory using the address signal and control signal. (2) DMA access Write the data in the FIFO buffer memory from the CPU's built-in DMAC or dedicated DMAC, or read the data from the FIFO buffer memory. USB communication is executed by a little endian. A byte endian swap function is provided in the FIFO port access. For 16-bit access, the endian can be changed according to what is written to the register. 1.6.2.3 FIFO buffer memory access method from DMAC To access the FIFO buffer memory through the DMA access, select an access method from the following: (1) Method of using common bus with CPU (2) Method in which dedicated bus (split bus) is used 1.6.3 USB event The controller notifies the events regarding USB operations to the user system through the interrupt. It also notifies that the DMA interface can access the buffer memory of the selected pipe by asserting the DREQ signal. Depending on what the software writes, interrupt notification activation can be selected for the type and factor. Rev1.01 Oct 17, 2008 Page 10 of 183 Confidential R8A66597FP/DFP/BG 1.6.4 USB data transfer All types of data transfer of USB communication, such as control transfer, bulk transfer, interrupt transfer and isochronous transfer, are possible with this controller. The following are the pipe resources for each transfer type: (1) Control transfer dedicated pipe - 1 (2) Interrupt transfer dedicated pipes - 4 (3) Bulk transfer dedicated pipes - 3 (4) Bulk transfer or isochronous transfer selection pipes - 2 Write the USB transfer requirements for each pipe, such as transfer type, endpoint address, maximum packet size, etc., according to the user system. This controller is equipped with an 8.5KB buffer memory. Allocate the buffer memory according to the user system or execute the settings such as buffer operation mode, for the bulk transfer dedicated pipe, and bulk transfer or isochronous transfer selection pipe. In buffer operations mode, high-performance data transfer with low interrupt frequency is possible by using a double buffer configuration or continuous transfer function of the data packet. A transfer completion function has been added, using the transaction counter function for efficient data transfer rates of bulk and isochronous transfer pipes. The user system control CPU and DMA controller access the buffer memory through three FIFO port registers. 1.6.5 Interface for access from DMAC The DMA interface is the data transfer between the user system and this controller, in which the DxFIFO port is used, and it is a data transfer that does not use the CPU. This controller is equipped with 2-ch DMA interface and includes the following functions: (1) Transfer end notification function corresponding to the transfer end signal (DEND signal) (2) FIFO buffer auto clear function while receiving a zero-length packet This controller is equipped with an interface compatible with the two types of DMA transfers given below: (1) Cycle Steal Transfer Assert and negate of the DREQ pin is repeatedly transmitted for one data transmission (1 byte/1 word). (2) Burst Transmission This is a transmission in which the DREQ pin is asserted (not negated) until the transmission is completed, due to the pipe buffer memory area allocated to the FIFO port or DEND signal. "CS_N, RD_N and WR_N" or DACK_N can be selected as the handshake signal (pin) of the DMA interface. High-performance DMA transmission is possible in the DMA transmission by a split bus by modifying the data setup timing using an OBUS bit operation of the DMAxCFG register. 1.6.6 SOF pulse output function This controller is equipped with an SOF pulse output function that notifies the SOF packet send/receive timing. When the Host Controller function is selected, a pulse is output from the SOF_N pin at sending the SOF packet. When the Peripheral Controller function is selected, a pulse is output from the SOF_N pin at receiving the SOF packet. When the SOF packet is damaged, a pulse is output within the specified period according to the SOF interpolation timer. Rev1.01 Oct 17, 2008 Page 11 of 183 Confidential R8A66597FP/DFP/BG 1.6.7 Importing the external devices This controller is equipped with the external devices listed below. Also, as the VBUS pin has 5V-tolerant, the user system can connect the VBUS signal directly to this controller. (1) Resistors necessary in D+ and D-line control The following D+ and D- resistors necessary for USB communication are installed: D+ pull-up resistor (for Peripheral operations) D+ pull-down resistor (for host operations) D+ and D- termination resistors (for Hi-Speed operations) D+ and D- output resistors (for Full-Speed and Low-Speed operations) (2) 48MHz and 480MHz PLL Operations can be executed by selecting one of the three types of external clocks (12MHz/24MHz/48MHz). (3) 3.3V 1.5V regulator 1.5V core power is generated in this controller. In the system where a 3.3V interface power is used, this controller can be operated on a single power supply. Rev1.01 Oct 17, 2008 Page 12 of 183 Confidential R8A66597FP/DFP/BG 2 Register Design of Register Table 1 Bit number: Each register is connected to the 16-bit internal bus. Odd address are from b15 to b8, and even address are from b7 to b0. 2 Status after reset: Indicates the register initial status immediately after the reset operation. A hardware reset is the initialization status when the external reset signal is entered from the RST_N pin. A USB reset is the initialization status when a USB bus reset is detected by the controller. Significant points in the reset operation are mentioned in the notes. "-" indicates the status of retained user settings without any controller operations. "?" indicates the status when the value is not determined. 3 Software access conditions: Conditions when the register is accessed by the software. 4 Hardware access conditions: Conditions when the register is accessed by the controller during operations other than reset: R......Read only W......Write only R/W...Read/Write R(0)..."0" Read only W(1)..."1" Write only 5 Remarks: Remarks and detailed description item number. H...When the Host Controller function is selected P...When the Peripheral Controller function is selected 6 Name: This is the bit symbol and bit name. 7 Function: This is the description of the function. When there is no particular rejection, the value during read is the value written by the software or hardware. Example: The shaded portions are unassigned. Fix to"0". 1 Bit Number Bit Symbol 2 Hardware reset USB reset Bit 15 14 13 12 15 ? ? 14 13 12 A bit B bit C bit 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 Name Unassigned. Fix to "0". A bit AAA enabled B bit BBB operation C bit CCC control 6 Function 0: Operations disabled 1: Operations enabled 0: Low output 1: High output 0: 1: 7 Software Hardware Remarks Writing disabled when P R/W R R(0)/W(1) 3 R W R 4 5 Remarks Rev1.01 Oct 17, 2008 page 13 of 183 R8A66597FP/DFP/BG 2.1 Register List The controller register list is shown in Table 2.1. Table 2.1 Register List Address 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 Rev1.01 Symbol SYSCFG0 SYSCFG1 SYSSTS0 SYSSTS1 DVSTCTR0 DVSTCTR1 TESTMODE PINCFG DMA0CFG DMA1CFG CFIFO D0FIFO D1FIFO CFIFOSEL CFIFOCTR Name System configuration control register Port1 System configuration control register Port0 System configuration status register Port1 System configuration status register Port0 Device control register Port1 Device control register Test mode register Data pin configuration register DMA0 Pin configuration register DMA1 Pin configuration register CFIFO Port register D0FIFO Port register D1FIFO Port register CFIFO Port selection register CFIFO Port control register Index D0FIFOSEL D0FIFOCTR D1FIFOSEL D1FIFOCTR INTENB0 INTENB1 INTENB2 BRDYENB NRDYENB BEMPENB SOFCFG INTSTS0 INTSTS1 INTSTS2 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR D0FIFO Port selection register D0FIFO Port control register D1FIFO Port selection register D1FIFO Port control register Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 BRDY Interrupt enable register NRDY Interrupt enable register BEMP Interrupt enable register SOF Output configuration register Interrupt status register0 Interrupt status register1 Interrupt status register2 BRDY Interrupt status register NRDY Interrupt status register BEMP Interrupt status register Frame number register Microframe number register USB address register USB request type register USB request value register USB request index register USB request length register DCP configuration register DCP maximum packet size register DCP control register Pipe window selection register Pipe configuration register Pipe buffer specification register Pipe maximum packet size register Pipe period control register Pipe1 Control register Pipe2 Control register Pipe3 Control register Oct 17, 2008 page 14 of 183 R8A66597FP/DFP/BG Address 76 78 7A 7C 7E 80 82-8E 90 92 94 96 98 9A 9C 9E A0 A2 A4-CE D0 D2 D4 D6 D8 DA DC DE E0 E2 E4 E6 Symbol PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR PIPE1TRE PIPE1TRN PIPE2TRE PIPE2TRN PIPE3TRE PIPE3TRN PIPE4TRE PIPE4TRN PIPE5TRE PIPE5TRN DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD7 DEVADD6 DEVADD7 DEVADD8 DEVADD9 DEVADDA Name Pipe4 Control register Pipe5 Control register Pipe6 Control register Pipe7 Control register Pipe8 Control register Pipe9 Control register Pipe1 Transaction counter enabled register Pipe1 Transaction counter register Pipe2 Transaction counter enabled register Pipe2 Transaction counter register Pipe3 Transaction counter enabled register Pipe3 Transaction counter register Pipe4 Transaction counter enabled register Pipe4 Transaction counter register Pipe5 Transaction counter enabled register Pipe5 Transaction counter register Device address 0 configuration register Device address 1 configuration register Device address 2 configuration register Device address 3 configuration register Device address 4 configuration register Device address 5 configuration register Device address 6 configuration register Device address 7 configuration register Device address 8 configuration register Device address 9 configuration register Device address A configuration register Index Nothing is assigned to the shaded portions. Do not access. Rev1.01 Oct 17, 2008 page 15 of 183 R8A66597FP/DFP/BG 2.2 Bit Symbol List A list of controller bit symbols is shown in Table 2.2. Table 2.2 Bit Symbol List Addr 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E Register name 15 14 13 Odd numbers 12 11 10 SCKE 9 8 7 HSE HSE 6 DCFM 5 Even numbers 4 3 2 1 0 USBE SYSCFG0 XTAL XCKE PLLC SYSCFG1 CNTFLG SYSSTS0 OVCMON SYSSTS1 OVCMON DVSTCTR0 HNPBTOA DVSTCTR1 UTEST PINCFG LDRV DMA0CFG DREQA BURST DMA1CFG DREQA BURST CFIFO D0FIFO D1FIFO CFIFOSEL CFIFOCTR RCNT BVAL REW BCLR DRPD DPRPU PCSDIS LPSME DRPD HDDM HDDM EXTLP0 VBOUT WKUP RWUPE USBRST RESUME UACT VBOUT RWUPE USBRST RESUME UACT IDMON DACKA DACKA DFORM DFORM CFPORT D0FPORT D1FIPORT DENDA PKTM DENDA PKTM DENDE DENDE LNST LNST RHST RHST UTST INTA OBUS OBUS MBW FRDY BIGEND ISEL DTLN CURPIPE D0FIFOSEL REW DCLRM DREQE MBW BIGEND BCLR FRDY D1FIFOSEL REW DCLRM DREQE MBW BIGEND D1FIFOCTR BCLR FRDY INTENB0 RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE INTENB1 DTCHE ATTCHE OVRCRE BCHGE INTENB2 DTCHE ATTCHE OVRCRE BCHGE BRDYENB NRDYENB BEMPENB SOFCFG TRNENSEL D0FIFOCTR RCNT BVAL RCNT BVAL VBSE CURPIPE DTLN CURPIPE DTLN EOFERRE SIGNE EOFERRE SACKE BRDYM VBSTS PIPEBRDYE PIPENRDYE PIPEBEMPE INTL EDGESTS SOFM VALID CTSQ INTSTS0 INTSTS1 INTSTS2 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR PIPESEL PIPECFG PIPEBUF PIPEMAXP PIPEPERI VBINT RESM OVRCR BCHG OVRCR BCHG SOFR DVST DTCH DTCH CTRT ATTCH ATTCH BEMP NRDY BRDY OVRN CRCE DVSQ EOFERR SIGN SACK EOFERR PIPEBRDY PIPENRDY PIPEBEMP FRNM UFRNM USBADDR bRequest wValue wIndex wLength CNTMD SHTNAK BSTS DEVSEL SUREQ CSCLR CSSTS SUREQCLR bmRequestType DIR MXPS CCPL PIPESEL PID SQCLR SQSET SQMON PBUSY PINGE TYPE BUFSIZE DEVSEL IFIS BFRE DBLB CNTMD SHTNAK MXPS DIR BUFNMB EPNUM IITV Rev1.01 Oct 17, 2008 page 16 of 183 R8A66597FP/DFP/BG Register name Odd numbers 12 11 CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS CSSTS Addr 15 BSTS BSTS BSTS BSTS BSTS BSTS BSTS BSTS BSTS 14 INBUFM INBUFM INBUFM INBUFM INBUFM 13 CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR CSCLR 10 ATREPM ATREPM ATREPM ATREPM ATREPM 9 ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM ACLRM 8 SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR SQCLR 7 SQSET SQSET SQSET SQSET SQSET SQSET SQSET SQSET SQSET 6 SQMON SQMON SQMON SQMON SQMON SQMON SQMON SQMON SQMON 5 PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY PBUSY Even numbers 4 3 2 1 PID PID PID PID PID PID PID PID PID 0 70 PIPE1CTR 72 PIPE2CTR 74 PIPE3CTR 76 PIPE4CTR 78 PIPE5CTR 7A PIPE6CTR 7C PIPE7CTR 7E PIPE8CTR 80 PIPE9CTR 828E 90 PIPE1TRE 92 PIPE1TRN 94 PIPE2TRE 96 PIPE2TRN 98 PIPE3TRE 9A PIPE3TRN 9C PIPE4TRE 9E PIPE4TRN A0 PIPE5TRE A2 A4CE D0 D2 D4 D6 D8 DA DC DE E0 E2 E4 PIPE5TRN TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT TRENB TRCLR TRNCNT DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD5 DEVADD6 DEVADD7 DEVADD8 DEVADD9 DEVADDA HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HPPHUB HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT HUBPORT USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD USBSPD RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT RTPORT E6 Rev1.01 Oct 17, 2008 page 17 of 183 R8A66597FP/DFP/BG 2.3 System Configuration Control System configuration control register (SYSCFG0) 15 14 13 12 11 10 9 XTAL XCKE PLLC SCKE 0 0 0 ? 0 0 ? ? ? Bit Name 8 ? ? 7 HSE 0 Function Specifies the clock frequency entered from the XIN pin. 00: 12MHz input 01: 24MHz input 10: 48MHz input 11: Reserved Specifies whether the oscillation buffer operations are disabled or enabled. 0: Oscillation buffer operations disabled 1: Oscillation buffer operations enabled 6 5 4 DCFM DRPD DPRPU 0 0 0 3 ? ? Software 15-14 XTAL XIN clock selection R/W R 13 12 XCKE Oscillation buffer enabled Unassigned. Fix to "0". R/W R Specifies whether 48MHz PLL operations are PLLC disabled or enabled. 11 48MHz PLL Operations enabled 0: PLL operations disabled 1: PLL operations enabled Specifies whether 48MHz clock can be provided to SCKE USB block. 10 USB block clock enabled 0: Cannot provide clock to USB block 1: Can provide clock to USB block 9-8 Unassigned. Fix to "0". Specifies whether Port0 Hi-Speed operations are disabled or enabled. 0: Hi-Speed operations disabled HSE (When a Peripheral function is selected: 7 Port0 Hi-Speed Operations Full-Speed, enabled When the Host function is selected: Full-Speed/Low-Speed) 1: Hi-Speed operations enabled (Controller detects communication speed) Specifies the controller functions. DCFM 6 0: Peripheral Controller function selection Controller functions selection 1: Host Controller function selection Specifies whether D+/D- line pull-down for the Host DRPD Controller function of Port0 is disabled or enabled. 5 D+/D-line resistance control of 0: Pull-down disabled Port0 1: Pull-down enabled Specifies D+ line pull-up for the Peripheral DPRPU Controller function of Port0 is disabled or enabled. 4 D+line resistance control 0: Pull-up disabled 1: Pull-up enabled 3-1 Unassigned. Fix to "0". Specifies USB block operations are disabled or USBE enabled. 0 USB block operations enabled 0: USB block operations disabled 1: USB block operations enabled Remarks None R/W R/W R/W R/W R/W R R/W R H (Write to "0" when P) P (Write to "0" when H) R/W R R/W R R/W R Rev1.01 Oct 17, 2008 page 18 of 183 R8A66597FP/DFP/BG 2.3.1 XIN clock selection bit (XTAL) In this bit, write the value corresponding to the quartz crystal or oscillator connected to the XIN pin. This controller determines the increasing multiples of 48MHz PLL according to the setup value of this bit. This bit is set immediately after a hardware reset. Do not modify it during controller operations. 2.3.2 Oscillation buffer enable bit (XCKE) Write "1" to this bit to enable the oscillation buffer operations of this controller. Write "0" to disable the oscillation buffer operations. Do not write "XCKE=0" for the time (time when "CNTFLG=1" is displayed) when clock restoration process is carried out by the controller. Write "XCKE=1" to end the clock restoration process. 2.3.3 2.3.4 48MHz PLL operations enabled bit (PLLC) Write "1" to this bit to enable this controller's 48MHz PLL operations. Write "0" to disable them. USB block clock enabled bit (SCKE) Write "1" to this bit to enable this controller's clock supply to the USB block. Write "0" to disable it. When "0" is written to this bit, the registers that can be written to are shown in Table 2.3. Other registers cannot be written. Each register can be read when "0" is written to this bit. Table 2.3 List of Registers That Can Be Written by the Software When "SCKE=0" Address 00H 02H 0EH Register name SYSCFG0 SYSCFG1 PINCFG 2.3.5 Hi-Speed operations enabled bit (HSE) Write "1" to this bit to enable Hi-Speed operations for Port0. When "HSE=1" is written, this controller operates Port0 with Hi-Speed or Full-Speed depending on the reset handshake result. 2.3.5.1 Host Controller function selection When "HSE=0" is written, the port operates at Low-Speed or Full-Speed. When it is detected that a Low-Speed peripheral device is attached to the port, always write "HSE=0". When "HSE=1" is written, this controller executes the reset handshake protocol and, depending on its result, the port operates at Hi-Speed or Full-Speed automatically. This bit can be modified "after attach detection (ATTCH interrupt detection) and before the USB bus reset (before writing "USBRESET=1")". Rev1.01 Oct 17, 2008 page 19 of 183 R8A66597FP/DFP/BG 2.3.5.2 Peripheral Controller function selection When "HSE=0" is written, the controller executes Full-Speed operations. When "HSE=1" is written, the controller executes reset handshake protocol and, depending on the result, Hi-Speed or Full-Speed operations are executed automatically. This bit can be modified when "DPRPU=0". 2.3.6 Controller function selection bit (DCFM) Set this bit to specify the Host Controller function or Peripheral Controller function for the controller. This bit can be modified when "DPRPU=0" and "DRPD=0". 2.3.7 D+, D- line resistance control for Port0 (DRPD and DPRPU) Settings related to USB data bus resistance of Port0 are given in Table 2.4. Select USB data bus resistance in DRPD and DPRPU bits. Table 2.4 Port0 USB Data Bus Resistance Control Write DRPD 0 0 1 1 Contents DPRPU 0 1 0 1 D- Line Open Open D+ Line Open Pull-up USB data bus resistance control Remarks Execute these settings when the controller is operated as the Peripheral Controller. Execute these settings when the controller is operated as the Host Pull-down Pull-down Controller. Pull-down Pull-up Write disabled 2.3.7.1 Port0 pull-down resistance control (DRPD) for the Host Controller function If "1" is written to this bit while selecting the Host Controller function, the controller pulls down the Port0 D+ and Dlines. When selecting the Host Controller function, write "1" to this bit. 2.3.7.2 Port0 D+ pull-up resistance control (DPRPU) for the Peripheral Controller function If "1" is written to this bit while selecting the Peripheral Controller function, the controller pulls up the Port0 D+ line to 3.3V, and can notify the USB host of an "attach". The controller cancels the D+ line pull-up if the bit setting is changed from "1" to "0", and the status for the USB Host can be shown as detached. Set this bit to "1" when selecting the Peripheral Controller function. Rev1.01 Oct 17, 2008 page 20 of 183 R8A66597FP/DFP/BG 2.3.8 USB block operations enabled bit (USBE) This controller's USB block operations can be enabled/disabled by writing to this bit. If the bit is modified from "USBE=1" to "USBE=0", the controller initializes the bits shown in Table 2.5 and Table 2.6. Table 2.5 List of Registers Initialized When Writing "USBE=0" (When the Peripheral Controller function ("DCFM=0" setting) is selected) Register Name SYSSTS0 SYSSTS1 DVSTCTR0 DVSTCTR0 INTSTS0 USBADDR USBREQ USBVAL USBINDX USBLENG Bit name LNST RHST DVSQ USBADDR bRequest bmRequestType wValue wIndex wLength Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Value retained while selecting the Host Controller function Remark Value retained while selecting the Host Controller function Table 2.6 List of Registers Initialized When Writing "USBE=0" (While the Host Controller function ("DCFM=1" setting) is selected) Register Name DVSTCTR0 DVSTCTR0 FRMNUM UFRMNUM Bit Name RHST FRNM UFRNM Value retained while selecting the Peripheral Controller function Value retained while selecting the Peripheral Controller function Remark This bit can be modified when "SCKE=1". When selecting the Host Controller function, write "DPRD=1", reject the LNST bit chattering, confirm that the USB bus is stable, and then write "USBE=1". Rev1.01 Oct 17, 2008 page 21 of 183 R8A66597FP/DFP/BG Port1 System configuration control register [SYSCFG1] 15 14 13 12 11 10 9 8 7 CNTFLG PCSDIS LPSME HSE ? ? ? 0 ? ? 0 0 0 ? ? ? ? ? Bit Name Function 6 ? ? 5 DRPD 0 - 4 ? ? 3 ? ? 2 ? ? Software Hardware Remarks 15-13 Unassigned. Fix to "0". 12 CNTFLG Auto clock monitor Displays whether auto clock setup process is currently being executed. 0: Auto clock process complete or clock stopped 1: Auto clock processing R W 11-10 Unassigned. Fix to "0". Specifies whether restoration from low power sleep PCSDIS mode is possible due to fall in CS_N. 9 Restoration from low power sleep 0: Restoration enabled due to CS_N mode by CS N disabled 1: Restoration disabled due to CS_N Specifies whether the controller can shift to low LPSME power sleep mode when the clock is being stopped. 8 Low power sleep mode enabled 0: Low power sleep mode disabled 1: Low power sleep mode enabled Enables Port1 Hi-Speed operations when the Host HSE Controller function is selected. 7 Port1 Hi-Speed operations enabled 0: Hi-Speed operations disabled (Full-/Low-Speed) 1: Hi-Speed operations enabled (controller detects) 6 Unassigned. Fix to "0". Specifies whether D+/D- line pull-down for the Host DRPD Controller function of Port1 is disabled or enabled 5 D+/D- line resistance control of 0: Pull-down disabled Port1 1: Pull-down enabled 4-0 Unassigned. Fix to "0". Remarks None R/W R R/W R H (Write to "0" when P) H (Write to "0" when P) R/W R R/W R 2.3.9 Auto clock monitoring bit (CNTFLG) This bit sets "1" when the clock restoration process is being executed by the controller. This bit is modified from "0" to "1" when the clock restoration process by the controller is started, and after the clock is restored and when "SCKE=1", "1" is modified to "0". 2.3.10 CS_N Restoration disabled bit (PCSDIS) This bit enables or disables the falling edge of CS_N as an event to shift the controller from low power sleep mode to normal status. Refer to Table 2.7 for the difference in restoration events according to the setup value of this bit. Rev1.01 Oct 17, 2008 page 22 of 183 R8A66597FP/DFP/BG 2.3.11 Low power sleep mode enabled bit (LPSME) This controller enters low power sleep mode when the oscillation buffer is stopped ("XCKE=0" setting) and when "LPSME=1". The standby power can be further reduced compared to when "LPSME=0" and in the oscillation buffer stopped mode. The two types of events that help this controller restore to normal clock operating status from the low power sleep mode, which was caused by "LPSME=1" and "XCKE=0", are given below. Table 2.7 Restoration Event from Low Power Sleep Mode ("LPSME=1" and "XCKE=0") Controller Function Selection (DCFM Bit Setup Value) When selecting the Peripheral Controller function Conditions If writing "PCSDIS=0" If writing "PCSDIS=1" When selecting the Host Controller function If writing "PCSDIS=0" If writing "PCSDIS=1" Restoration Events (1) RESM interrupt detection if writing "RSME=1" (2) VBINT interrupt detection if writing "VBSE=1" (3) CS_N signal assert by dummy reading from CPU (1) RESM interrupt detection if writing "RSME=1" (2) VBINT interrupt detection if writing "VBSE=1" (1) BCHG interrupt detection in the port written as "BCHGE=1" (2) CS_N signal assert by dummy reading from CPU (1) BCHG interrupt detection in the port written as "BCHGE=1" Write "LPSME=1" when "XCKE=1". When writing "LPSME=1", writing "XCKE=0" makes this controller enter low power sleep mode, and access to the controller is disabled for 10s. Therefore, exit from low power sleep mode with a dummy reading from the CPU after at least 10s have elapsed after writing "XCKE=0". When the controller is shifted to low power sleep mode, the value in the FIFO buffer is lost. While using the controller with "LPSME=1", read the FIFO contents or clear the FIFO buffer before writing "XCKE=0". 2.3.12 Hi-Speed operations enabled bit (HSE) Hi-Speed operations are enabled for Port1 by writing "1" to this bit". If "HSE=1" written, the controller operates Port1 at Hi-Speed or Full-Speed according to the reset handshake result. 2.3.12.1 Selecting the Host Controller function Refer to 2.3.5.1. 2.3.12.2 Selecting the Peripheral Controller function Write "0" to this bit. Port1 cannot be used when the Peripheral Controller function is in use. 2.3.13 D+, D- line resistor control bit for Port1 (DRPD) The settings for the Port1 USB data bus resistor are shown in Table 2.8. Select the USB data bus resistance using the SYSCFG1 register DRPD bit. Table 2.8 Port1 USB Data Bus Resistance Control DRPD 0 1 Remarks When Port1 is not used Write to this status during operations as Host Pull-down Pull-down Controller. D- Line Open D+ Line Open The controller pulls down the Port1 D+ and D- lines if "1" is written to this bit when selecting the Host Controller function. Rev1.01 Oct 17, 2008 page 23 of 183 R8A66597FP/DFP/BG 2.4 System Configuration Status Port0 System Configuration Status Register [SYSSTS0] 15 14 13 12 11 10 9 8 OVCMON ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bit Name 7 ? ? 6 ? ? 5 ? ? 4 ? ? 3 ? ? Function Sets the input status of OVCUR0A and OVCUR0B pins. 00: OVCUR0A=Low, OVCUR0B=Low 01: OVCUR0A=Low, OVCUR0B=High 10: OVCUR0A=High, OVCUR0B=Low 11: OVCUR0A=High, OVCUR0B=High Displays the status of UACT bit setting in response to Port0 operations 0: (micro) SOF issuance stopped 1: (micro) SOF issuance continued Sets the input status of ID0 pin. 0: ID0=Low 1: ID0=High Sets the USB line status of Port0. Refer to the detailed explanation. Software 15-14 OVCMON OVCUR0A, OVCUR0B pin monitor R W 13-6 Unassigned. Fix to "0". 5 SOFEA Port 0 HOST SOF active monitor R W 4-3 Unassigned. Fix to "0". 2 1-0 IDMON ID pin monitor LNST Port0 USB data line interface monitor R R W W Remarks None 2.4.1 OVCUR0A, OVCUR0B pin monitor bit (OVCMON) The controller sets the OVCUR0A pin status to bit 15 of this register, and the input status of OVCUR0B pin to bit 14. 2.4.2 Port0 HOST SOF Active Monitor Bit (SOFEA) When the UACT bit is set to "1" by software while the Host Controller function is valid, the controller displays "1" at this bit, puts PORT0 in the USB bus enabled status, and outputs SOF. When the UACT bit is set to "0" by software, the controller goes to the idle status after SOF is output, and displays "0" at this bit. When a suspend is executed, after the UAC bit is cleared to "0" by software, this bit can be used to confirm that the controller outputs the last SOF to Port0 2.4.3 ID0 pin monitor bit (IDMON) The controller sets the input status of the ID0 pin to this bit. 2.4.4 Line status monitor bit (LNST) USB data bus line status table of the controller is shown in Table 2.9. The controller monitors the Port0 USB data bus line status (D+ and D- line) in the SYSSTS0 register LNST bit. Refer to this LNST bit after the "attach" process (write "DPRPU=1") when the Peripheral Controller function is selected, and after pull-down is enabled (write "DRPD=1") when the Host Controller function is selected. Rev1.01 Oct 17, 2008 page 24 of 183 R8A66597FP/DFP/BG Table 2.9 USB Data Bus Line Status Low-Speed operations (Only Full-Speed Hi-Speed LNST [1] LNST [0] when the Host Chirp operations operations operations Controller function is selected) 0 0 SE0 SE0 Squelch Squelch 0 1 K-State J-State Unsquelch Chirp J 1 0 J-State K-State Invalid Chirp K 1 1 SE1 SE1 Invalid Invalid Chirp: Reset handshake protocol being executed in Hi-Speed operations enabled status (HSE="1") Squelch: SE0 or idle status Unsquelch: Hi-Speed J State or Hi-Speed K State Chirp J: Chirp J-State Chirp K: Chirp K-State Rev1.01 Oct 17, 2008 page 25 of 183 R8A66597FP/DFP/BG Port1 System Configuration Status Register [SYSSTS1] 15 14 13 12 11 10 9 8 OVCMON ? 0 ? ? ? ? ? ? ? 0 ? ? ? ? ? ? Bit Name 7 ? ? Function 6 ? ? 5 SOFEA 0 4 ? ? 3 ? ? Software R 2 ? ? ? Hardware Remarks W OVCMON 15-14 OVCUR1 pin monitor 13-6 Unassigned. Fix to "0". 5 4-2 SOFEA Port1 HOST SOF active monitor Unassigned. Fix to "0". LNST Port1 USB data line status monitor Sets the status of OVCUR1 pin in bit 15. Bit 14 is fixed to "0". 00: OVCUR1=Low 10: OVCUR1=High Displays the status of UACT bit setting in response to Port1 operations 0: (micro) SOF issuance stopped 1: (micro) SOF issuance continued R W 1-0 Sets the Port1 USB line status. Refer to the detailed explanation. R W H (Read value is invalid when P) Remarks None 2.4.5 OVCUR1 pin monitor bit (OVCMON) The controller sets the OVCUR1 pin status to bit 15 of this resister. Bit 14 is fixed to "0". 2.4.6 Port1 HOST SOF Active Monitor Bit (SOFEA) When the UACT bit is set to "1" by software while the Host Controller function is valid, the controller displays "1" at this bit, puts PORT1 in the USB bus enabled status, and outputs SOF. When the UACT bit is set to "0" by software, the controller goes to the idle status after SOF is output, and displays "0" at this bit. When a suspend is executed, after the UAC bit is cleared to "0" by software, this bit can be used to confirm that the controller outputs the last SOF to Port1 2.4.7 Line status monitor bit (LNST) The controller monitors the USB data bus line status (D+ line and D- line) of Port1 in the SYSSTS1 register LNST bit. Each LNST bit consists of two bits. Refer to Table 2.9 for the meaning of each bit. The Port1 LNST bit is valid only when the Host Controller function is selected. Refer to the LNST bit after pull-down is enabled (write "DRPD=1") while selecting the Host Controller function. Rev1.01 Oct 17, 2008 page 26 of 183 R8A66597FP/DFP/BG 2.5 USB Signal Control Device state control register [DVSTCTR0] 15 14 13 12 11 10 ? ? Bit ? ? ? ? Name ? ? 9 8 7 6 5 4 HNPBTOA EXTLP0 VBOUT WKUP RWUPE USBRST RESUME UACT 0 0 0 0 0 0 0 0 0 Function 3 ? ? 2 0 - Software Hardware 15-12 Unassigned. Fix to "0". HNPBTOA Used for HNP switch from Peripheral to Host when HNP (Host Negotiation controller is used as On-The-Go (OTG) B-Device. 11 Protocol) B Device Host 0: Normal operations transition control bit 1: Enabled to from OTG Peripheral to Host EXTLP0 Controls the status to be output to the EXTLP0 pin. 10 EXTLP0 R/W pin output 0: EXTLP0 low output (default) control 1: EXTLP0 high output VBOUT Controls the status to be output to the VBOUT0 pin. 9 VBOUT0 R/W pin output 0: VBOUT0=Low output (Default) control 1: VBOUT0=High output Specifies whether the remote wakeup (resume signal output) is disabled/enabled when the Peripheral Controller WKUP 8 function is in use. R/W(1) Wakeup output 0: Remote wakeup signal not output 1: Remote wakeup signal output Specifies whether detection of remote wakeup (resume RWUPE signal output) from Peripheral Device connected to PORT0 7 Remote wakeup detection is disabled/enabled when Host Controller function is in use. R/W disabled 0: Down port remote wakeup output disabled 1: Down port remote wakeup enabled USBRST Controls the USB reset output control of Port0. 6 Port0 USB bus reset 0: Not output R/W output 1: USB bus reset output signal output Controls the resume output of Port0. RESUME 5 R/W 0: Not output Port0 resume output 1: Resume signal output Enables USB bus operations. 0: Down Port operations disabled (SOF/MicroSOF delivery UACT 4 disabled) R/W Port0 USB bus enabled 1: Down Port operations enabled (SOF/MicroSOF delivery enabled) 3 Unassigned. Fix to "0". 2-0 RHST Port0 reset handshake Displays the Port0 reset handshake status. Refer to the detailed explanation. R R R R/W(0) P (Write to "0" when H) R H (Write to "0" when P) H (Write to "0" when P) H (Write to "0" when P) H (Write to "0" when P) R R/W(1) R/W(0) W Remarks None Rev1.01 Oct 17, 2008 page 27 of 183 R8A66597FP/DFP/BG 2.5.1 HNP (Host Negotiation Protocol) B-Device Transition Control Bit (HNPBTOA) When using the controller as the On-The-Go (OTG) B-Device, set this bit to "1" during the HNP switch from Peripheral to Host. When this bit is "1", the controller's internal peripheral control circuit holds the suspend status until the HNP process is completed, regardless of "DPRPU=0" or "DCFM=1" software settings. In addition, the Resume (RESM) interrupt will not be generated even if a falling edge is detected on the D+ signal. Only program this bit to "1" while operating the controller as an OTG B-Device and the Peripheral Controller Function is in the suspend status. 2.5.2 EXTLP0 Pin Output Control Bit (EXTLP0) If "1" is written to this bit, the controller outputs High from the EXTLP0 pin. If "0" is writthen to the bit, it outputs Low. 2.5.3 VBOUT Pin Output Control Bit (VBOUT0) If "1" is written to this bit, the controller outputs High from the VBOUT0 pin. If "0" is writthen to the bit, it outputs Low. 2.5.4 Remote wakeup (resume signal output) enabled/disabled bit for the Peripheral Controller function (WKUP) If "1" is written to this bit while selecting the Peripheral Controller function, the controller outputs the remote wakeup signal to the Port0 USB bus. The controller manages the output time of the remote wakeup signal. If the software writes "1" to the WKUP bit, the controller outputs a "K-State" of 10ms and then changes the setting to "WKUP=0". According to the USB Specification Revision 2.0, the USB bus idle status should be maintained for at least 5ms until the remote wakeup signal is sent. Therefore, the controller outputs a K-State after waiting for 2ms, although "WKUP=1" is written immediately after detecting the suspend status. Write "1" to the WKUP bit only when the device state is suspend ("DVSQ=1xx") and when the remote wakeup is enabled from the USB Host. Do not stop the internal clock when "1" is written to the WKUP bit, irrespective of the suspend status (write "WKUP=1" in the "SCKE=1" status). 2.5.5 Port0 remote wakeup detection disabled/enabled bit for the Host Controller function (RWUPE) If "1" is written to this bit while selecting the Host Controller function, the controller detects the remote wakeup signal (K-State during 2.5s) from the Peripheral device connected to the port and executes the resume process (K-State drive). When "0" is written to this bit, the controller ignores the remote wakeup signal (K-State) from the Peripheral device connected to the port, irrespective of detecting it. When "1" is written to this bit, do not stop the internal clock even if it is in suspend status (keep in "SCKE=1" status). Do not reset the USB bus (write "USBRST=1") in suspend status. This is disabled in the USB Specification Revision 2.0. 2.5.6 Port0 USB bus reset output disabled/enabled bit for Host Controller function (USBRST) If writing "1" to this bit while selecting the Host Controller function, the controller drives the port SE0 drive and executes the USB bus reset process. In this case, if the HSE bit compatible to Port0 is "1", execute the reset handshake protocol. This controller continues with the SE0 output when "USBRST=1" (until the software writes "USBRST=0"). While "USBRST=1" (USB bus reset time), write the time based on the USB Specification Revision 2.0. The USB bus is not reset until this controller changes to "UACT=0" and "RESUME=0" when "1" is written to this bit in ("UACT=1") communicate or ("RESUME=1") resume status. Write "1" to the UACT bit simultaneously with the USB bus reset termination (write "USBRST=0"). Rev1.01 Oct 17, 2008 page 28 of 183 R8A66597FP/DFP/BG 2.5.7 Port0 resume signal output bit for the Host Controller function (RESUME) If "1" is written to this bit while selecting the Host Controller function, the controller drives Port0 to the K-State and executes resume output. The controller sets this bit to "1" when "RWUPE=1" and the remote wakeup signal is detected in the USB suspend status. The controller continues with the K-State output when "RESUME=1" (until the software writes "RESUME=0"). While "RESUME=1" (resume time), write the time based on the USB Specification Revision 2.0. Write "1" to this bit during the suspend process. Write "1" to the UACT bit and USB bus reset termination (write "USBRST=0") simultaneously. 2.5.8 Port0 USB bus operations enabled bit for the Host Controller function (UACT) If "1" is written to this bit while selecting the Host Controller function, the controller changes the status of Port0 to USB bus enabled status, outputs SOF, and sends/receives the data. Once the software writes "UACT=1", SOF output starts within one (micro) frame time. When the software writes "1" to this bit", the controller transfers to idle status after the (micro) SOF output. The controller write "1" to this bit in the following cases: (1) When the DTCH interrupt is detected during communication (if writing "UACT=1") (2) When the EOFERR interrupt is detected during communication (if writing "UACT=1") Write "1" to this bit while terminating the USB reset process (write "USBRST=0") or while terminating the suspension process (write "RESUME=0"). 2.5.9 Port0 reset handshake status bit (RHST) The controller sets the result of the Port0 reset handshake in this bit. The results of reset handshake are listed in Table 2.10. Table 2.10 USB Data Bus Line Status Bus Status RHST While selecting the Peripheral Controller function 000 100 010 011 Bit Value While selecting the Host Controller function 000 1xx 001 010 011 When powered or during disconnect During reset handshake When connecting to Low-Speed When connecting to Full-Speed When connecting to Hi-Speed 2.5.9.1 Selecting the Host Controller function While selecting the Host Controller function, the bit sets "100" when the software writes "USBRST=1". When "HSE=1" is selected for the port, the bit setss "111" when the controller detects a Chirp K from the Peripheral device. The controller writes the RHST bit value when the software writes "USBRST=0" to the port, and when the controller terminates the SE0 drive. When the software writes "UTST=1xxx" (when parameters are written for a host test), the bit sets "011". Rev1.01 Oct 17, 2008 page 29 of 183 R8A66597FP/DFP/BG 2.5.9.2 Selecting the Peripheral Controller function When "HSE=1" is set for the port, the bit shows "100" when the controller detects a USB bus reset. The controller then outputs Chirp K, and this bit shows "011" when Chirp JK is detected three times from the USB Host. After Chirp K is output, if it is not set to Hi-Speed within 2.5ms, the bit shows "010". When "HSE=0" is set for the port, the bit shows "010" when the controller detects the USB bus reset. A DVST interrupt is generated when the RHST bit is set to "0101" or "011" after the USB bus reset is detected by the controller. Rev1.01 Oct 17, 2008 page 30 of 183 R8A66597FP/DFP/BG Device state control register [DVSTCTR1] 15 14 13 12 11 10 ? ? Bit ? ? ? ? Name ? ? ? ? ? ? 9 VBOUT 0 - 8 ? ? 4 RWUPE USBRST RESUME UACT 0 0 0 0 - 7 6 5 3 ? ? 2 0 - Function Software Hardware 15-10 Unassigned. Fix to "0". Controls the status output to the VBOUT1 pin. VBOUT 0: VBOUT1=Low output (default) VBOUT pin output control 1: VBOUT1=High output Controls the remote wakeup detection allow/prohibited RWUPE from the Peripheral device connected to Port1. remote wakeup 7 Port1 0: Down port wakeup prohibited detection allowed 1: Down port wakeup allowed USBRST Controls the USB bus reset output of Port1. 6 Port1 USB bus reset 0: USB bus reset not output output 1: USB bus reset signal output Controls the resume output of Port1. RESUME 5 0: Resume no signal output Port1 resume output 1: Resume signal output Enables USB bus of Port1. UACT 4 0: Down port prohibited (SOF/SOF delivery prohibited) Port1 USB bus allowed 1: Down port allowed (SOF/SOF delivery allowed) 3 Unassigned. Fix to "0". Status or result of Port1 reset handshake of is set. 000: When powered or disconnected RHST 1xx: During reset handshake 2-0 Port1 reset handshake 001: When connecting to Low-Speed 010: When connecting to Full-Speed 011: When connecting to Hi-Speed 9 Remarks None R/W R H (Write to "0" when P) H (Write to "0" whenP) H (Write to "0" when P) H (Write to "0" when P) R/W R R/W R R/W R/W(1) R/W R R W H (Write to "0" when P) 2.5.10 Port1 remote wakeup detection allowed/prohibited bit for the Host Controller function (RWUPE) Refer to 2.5.5. 2.5.11 Port1 USB bus reset output disabled/enabled bit for the Host Controller function (USBRST) Refer to 2.5.6. 2.5.12 Port1 resume signal output bit for the Host Controller function (RESUME) Refer to 2.5.7. 2.5.13 USB bus operations enabled bit of Port1 for the Host Controller function (UACT) Refer to 2.5.8. Rev1.01 Oct 17, 2008 page 31 of 183 R8A66597FP/DFP/BG 2.5.14 Reset handshake status bit of Port1 (RHST) The controller displays the result of the Port1 reset handshake in this bit. The reset handshake results are shown in Table 2.10. Table 2.11 USB Data Bus Line Status Bus status RHST When the Peripheral Controller function is selected Bit value When the Host Controller function is selected 000 1xx 001 010 011 When powered or disconnected During reset handshake When connecting to Low-Speed When connecting to Full-Speed When connecting to Hi-Speed 2.5.14.1 Selecting the Host Controller function Refer to 2.5.9.1. 2.5.14.2 Selecting the Peripheral Controller function The port cannot be used while selecting the Peripheral Controller function, so do not refer to the value of this bit. Rev1.01 Oct 17, 2008 page 32 of 183 R8A66597FP/DFP/BG 2.6 Test Mode Test Mode Register [TESTMODE] 15 14 13 12 11 ? ? Bit UTST test mode ? ? ? ? Name ? ? ? ? 10 ? ? 9 ? ? 8 ? ? 7 ? ? Function 6 ? ? 5 ? ? 4 ? ? 3 0 - 2 Software Hardware Remarks 15-4 Unassigned. Fix it to "0". 3-0 Refer to detailed description. R/W R Remarks None 2.6.1 Test mode bit (UTST) The controller writes the value to this bit to output the USB test signal during Hi-Speed operations. The test mode operations of the controller are given in Table 2.12. Table 2.12 Test Mode Operations Test mode Normal operations Test_J Test_K Test_SE0_NAK Test_Packet Test_Force_Enable Reserved UTST bit settings When the Peripheral Controller When the Host Controller function function is selected is selected 0000 0000 0001 1001 0010 1010 0011 1011 0100 1100 1101 0101-0111 1110-1111 Rev1.01 Oct 17, 2008 page 33 of 183 R8A66597FP/DFP/BG 2.6.1.1 Selecting the Host Controller function When the Host Controller function is selected, writing to the bit is possible after writing "DRPD=1" corresponding to the test target port from Port0 and Port1. This bit is the common register for Port0 and Port1. The controller outputs the wave for the port where "DRPD=1" and "UACT=1" are written. When the Host Controller function is selected, the controller stops Hi-Speed operations for Port0 and Port1 by writing to the bit. Procedure to set the UTST bit in HOST mode is below: (1) Hardware reset (2) Clock activation (write to XTAL, wait until "XCKE=1" changes to "SCKE=1") (3) "DCFM=1" and "DPRD=1" (not necessary to write "HSE=1") (4) "USBE=1" (5) Write the value corresponding to the test contents in the UTST bit. (6) Write "1" to the UACT bit of the port to be tested Procedure to modify the UTST bit in HOST mode is below: (1) (In the status of above-mentioned (8)) "UACT=0" and "USBE=0" (2) "USBE=1" (3) Write the value corresponding to the test contents in the UTST bit. (4) Write "1" to the UACT bit of the port to be tested When writing "Test_SE0_NAK" ("1011"), the controller does not output the SOF packet related to the port for which "UACT=1" was written. When writing "Test_Force_Enable" ("1101"), the controller outputs the SOF packet related to the port for which "UACT=1" is written. The controller does not control the hardware associated with the detection when the mode is set, irrespective of detecting a Hi-Speed disconnection (detecting DTCH interrupt). When selecting the Host Controller function, set all pipe PID bits to "NAK" if writing to the UTST bit. After setting the test mode, reset the hardware when using normal USB communication. 2.6.1.2 Selecting the Peripheral Controller function When the Peripheral Controller function is selected, write this bit according to the set feature request from the USB Host during Hi-Speed communication. The controller does not move to suspend status if "0001" ~ "0100" is written to the bit when the Peripheral Controller function is selected. To perform normal USB communications after the test mode is set, execute a hardware reset first. Rev1.01 Oct 17, 2008 page 34 of 183 R8A66597FP/DFP/BG 2.7 Bus Interface Control Data pin configuration register [PINCFG] 15 14 13 12 11 10 LDRV 0 ? ? ? ? ? ? ? ? ? ? Bit 15 Name LDRV Output pin drive current control 9 ? ? 8 ? ? 7 ? ? Function 6 ? ? 5 ? ? 4 ? ? 3 ? ? 2 ? ? Software Hardware Remarks R/W R 0: When VIF=1.6-2.0V 1: When VIF=2.7-3.6V Sets active of interrupt output from INT_N pin. 0: Low active 1: High active 14-1 Unassigned. Fix to "0". 0 INTA INT_N active settings R/W R Remarks 2.7.1 Output pin drive current control bit (LDRV) For this bit, write the value that matches the VIF power supply. The following are the output pins to be controlled using the drive current according to this bit: SD7-0, D15-0, INT_N, DREQx_N, DENDx_N and SOF_N pins. Write to this bit after resetting the hardware and do not modify it during controller operations. 2.7.2 INT_N active setting bit (INTA) Set the active (low/high) for interrupt output from INT_N that matches the interrupt input specifications of the CPU for control. Write to this bit after resetting the hardware, and do not modify it during controller operations. Rev1.01 Oct 17, 2008 page 35 of 183 R8A66597FP/DFP/BG The DMA0CFG register is for the DMA0 interface input/output pin and to control the D0FIFO port. The DMA1CFG register is for the DMA1 interface input/output pin and to control the D1FIFO port. DMA0 pin configuration register [DMA0CFG] DMA1 pin configuration register [DMA1CFG] 15 14 13 12 11 10 DREQA BURST DACKA ? 0 0 ? ? 0 ? ? ? Bit 15 14 Name Unassigned. Fix to "0". DREQA DREQx_N signal polarity selection BURST Burst mode 9 0 - 8 DFORM 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 ? ? DENDA PKTM DENDE 2 OBUS 0 - Function Indicates the active of the DREQx_N pin. 0: Low active 1: High active For DxFIFO, specifies whether to access by cycle steal transfer or by burst transfer. 0: Cycle steal transfer 1: Burst transfer Specifies active of the DACKx_N pin. 0: Low active 1: High active Specifies the control signal while accessing the FIFO buffer by DMA. 000: Use address signal+RD_N/WRx_N signal (CPU bus) 010: Use DACKx_N+RD_N/WRx_N signal (CPU bus) 011: Use DACKx_N signal only (CPU bus) 100: Use DACKx_N signal (SPLIT bus) 001, 101, 110 and 111: Reserved Specifies active of DENDx_N pin 0: Low active 1: High active Specifies DEND output timing. 0: Assert DENDx_N signal in the transfer unit 1: Assert DENDx_N signal for every data transfer of the given buffer size Enables the input/output of DENDx_N signal. 0: DENDx_N signal disabled (Hi-z output) 1: DENDx_N signal enabled Disables the OBUS operations. 0: OBUS mode enabled 1: OBUS mode disabled Software Hardware Remarks R/W R 13 R/W R 12-11 Unassigned. Fix to "0". 10 DACKA DACKx_N signal polarity selection R/W R 9-7 DFORM DMA transfer signal selection R/W R 6 DENDA DENDx_N signal polarity selection PKTM DEND output packet mode DENDE DENDx_N signal enabled Unassigned. Fix to "0". OBUS OBUS operations disabled R/W R 5 R/W R 4 3 2 R/W R R/W R 1-0 Unassigned. Fix to "0". Remarks None Rev1.01 Oct 17, 2008 page 36 of 183 R8A66597FP/DFP/BG 2.7.3 DMA signal control If transferring data using the DMA interface, use the DMAxCFG register's BURST bit, PKTM bit, DENDE bit, and OBUS bit to select the DMA interface operation (assert/negate of DREQx_N /DENDx_N signal and DMA transfer mode settings) that is configured to the user system. The DMA signal is valid for access to the FIFO buffer assigned to the pipe selected by the DxFIFOSEL register CURPIPE bit (to be mentioned later). When the status of the pipe FIFO buffer changes to buffer ready (BRDY) status, this controller asserts the DREQx_N signal if "DREQE=1". 2.7.4 DREQx_N signal polarity selection bit (DREQA) Set active of DREQx_N pin in this bit. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.5 Burst mode bit (BURST) When the DMA controller executes a cycle steal transfer for DxFIFO, write "0" to this bit. The controller negates a DREQx_N signal for access to one word or one byte. When the DMA controller executes a burst transfer for DxFIFO, write "1" to this bit. The controller negates the DREQx_N signal for accessing the last one word or one byte of FIFO buffer. Do not modify the bit during pipe communication operations. 2.7.6 DACKx_N signal polarity selection bit (DACKA) In this bit, set active the DACKx_N pin. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.7 DMA transfer signal selection bit (DFORM) In this bit, set the control signal while accessing the FIFO buffer with the DMA controller. For the FIFO port, write to this bit when "CURPIPE=000" 2.7.8 DENDx_N signal polarity selection bit (DENDA) In this bit, set active the DENDx_N pin. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.9 DEND output packet mode bit (PKTM) Write the DEND output timing in this bit. When "0" is written to this bit, the controller asserts the DENDx_N signal when any of the following conditions are fulfilled: (1) During the last read access while reading the short packet data (2) During the last read access while reading the data completed at the transaction counter (TRNCNT) (3) If a zero-length packet is received when the FIFO buffer is empty When "1" is written to this bit, the controller asserts a DENDx_N output for every data transfer of the given FIFO buffer size. For the FIFO port, write to this bit when "CURPIPE=000". Rev1.01 Oct 17, 2008 page 37 of 183 R8A66597FP/DFP/BG 2.7.10 Input/Output enabled bit of the DENDx_N signal (DENDE) Set I/O enabled/disabled for the DENDx_N pin in this bit. For the FIFO port, write to this bit when "CURPIPE=000". 2.7.11 OBUS operation disabled bit (OBUS) In this bit, write OBUS operations to be enabled/disabled. When "0" is written to this bit, theSD7-0 of the split bus and DEND is always input/output enabled". When "1" is written to this bit, the SD7-0 of the split bus and DENDx_N are are enabled only when DACKx_N is active. While commonly using D0FIFO and D1FIFO in the split bus, write "1" to all the OBUS bits. Rev1.01 Oct 17, 2008 page 38 of 183 R8A66597FP/DFP/BG 2.8 FIFO Port CFIFO Port register [CFIFO] D0FIFO Port register [D0FIFO] D1FIFO Port register [D1FIFO] 15 14 13 12 11 0 Bit 15-0 0 0 Name FIFOPORT FIFO port 0 0 10 0 - 9 0 - 8 7 FIFOPORT 0 0 Function 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - Software Hardware Remarks R/W R/W Reads the received data from the FIFO buffer by accessing this bit, or writes the being transmitted data to the FIFO buffer. Remarks None 2.8.1 FIFO port control The Rx/Tx buffer memory of this controller is made up of a FIFO structure (FIFO buffer). Use the FIFO port register to access the FIFO buffer. The CFIFO port, D0FIFO port and D1FIFO port are the types of FIFO ports. Each FIFO port consists of port registers (CFIFO, D0FIFO and D1FIFO) that read or write the data from or to the FIFO buffer, registers (CFIFOSEL, D0FIFOSEL and D1FIFOSEL) that select the pipes assigned to FIFO port, and control registers (CFIFOCTR, D0FIFOCTR and D1FIFOCTR). The features of each FIFO port are as follows: (1) Access the FIFO buffer for DCP using the CFIFO port. (2) The FIFO buffer access using the DMA transfer can be done through the DxFIFO port. (3) DxFIFO port access by the CPU is also possible. (4) While using functions specific to the FIFO port, the pipe number (selected pipe) to be written to the CURPIPE bit cannot be modified (signal input/output to the pin related to DMA, etc.). (5) Registers containing the FIFO port do not affect the other FIFO ports. (6) Do not assign the same pipe to separate FIFO ports. (7) In the FIFO buffer status, there are two types of access rights: one assigned to the CPU, and the other to SIE. Access from the CPU is not possible when SIE has the rights to access the buffer memory. Rev1.01 Oct 17, 2008 page 39 of 183 R8A66597FP/DFP/BG 2.8.2 FIFO port bit (CFIFO, D0FIFO and D1FIFO) The controller accesses the FIFO buffer assigned to the pipe number written to the CURPIPE bit of various selected registers (CFIFOSEL, D0FIFOSEL or D1FIFOSEL). Access to this register is possible only when the FRDY bit of each control register (CFIFOCTR, D0FIFOCTR or D1FIFOCTR) shows "1" (or while this controller asserts DREQx_N). The valid bits of this register differ according to the setup value of the MBW and BIGEND bits. The valid bits are shown in Table 2.13. Table 2.13 FIFO Port Valid Bits MBW SetupValue 0 0 1 1 BIGEND Setup Value 0 1 0 1 b15-b8 Invalid N+0 byte N+1 byte N+0 byte b7-b0 N+0 byte Invalid N+0 byte N+1 byte If writing "MBW =0", the N+0 byte as shown in Table 2.13 can be accessed. During read, access the 16-bit width for addresses 1H, 18 H and 1AH and use them as 8-bit data on N+0 byte as shown in Table 2.13. During write, access the 16-bit width for addresses 14H, 18H and 1AH (access by asserting both WR0_N and WR1_N. In this case, the controller ignores the N+1 byte as shown in Table 2.13), or access the 8-bit width for addresses 14H, 18H and 1AH (assert only WR0_N). If writing "MBW=1", the N+0 byte shown in Table 2.13 can be accessed. During read, access the 16-bit width for addresses 14H, 18H and 1AH. During write, access the 16-bit width for addresses 14H, 18H and 1AH (access by asserting WR0_N and WR1_N). Do not access the address for 15H, 19H and 1BH. Rev1.01 Oct 17, 2008 page 40 of 183 R8A66597FP/DFP/BG FIFO port selection register [CFIFOSEL] 15 14 13 12 11 10 RCNT REW MBW 0 0 ? ? ? 0 ? ? ? Bit 15 Name RCNT Read count mode REW Buffer pointer rewind 9 ? ? 8 BIGEND 0 - 7 ? ? 6 ? ? 5 ISEL 0 - 4 ? ? 3 ? ? 2 Function Specify read mode of CFIFOCTR DTLN. 0: DTLN bit clear by read of all the data received 1: DTLN bit count down for read of all the received data Specify "1" while rewinding the buffer pointer. 0: Do not rewind the buffer pointer 1: Rewind buffer pointer Specify the CFIFO port access bit width. 0: 8-bit width 1: 16-bit width Specify the CFIFO port byte endian. 0: Little endian 1: Big endian Software Hardware Remarks R/W R 14 R(0)/W R/W(0) 13-11 Unassigned. Fix to "0". 10 9 8 MBW CFIFO port access bit width Unassigned. Fix to "0". BIGEND FIFO port endian control R/W R R/W R 7-6 Unassigned. Fix to "0". Specify access direction of the FIFO port when DCP is ISEL selected in CURPIPE bit. 5 Access direction of the FIFO 0: This selects read from the buffer memory port when DCP is selected 1: This selects write to the buffer memory 4-3 Unassigned. Fix to "0". Specify the pipe number to access the CFIFO port. 0000: DCP CURPIPE 0001: Pipe1 2-0 FIFO port access pipe 0010: Pipe2 specification 1000: Pipe8 1001: Pipe9 Remarks None R/W R R/W R Rev1.01 Oct 17, 2008 page 41 of 183 R8A66597FP/DFP/BG 2.8.3 Read count mode (RCNT) When "0" is written to this bit, if all reception data of the FIFO buffer assigned to the pipe specified in the CURPIPE bit is read (when the data is read on one side of a double buffer), the controller clears the CFIFOCTR register DTLN bit to "0". When "1" is written to this bit, the controller counts the CFIFOCTR register DTLN bit whenever the data received from the FIFO buffer assigned to the specified bit is read. 2.8.4 Buffer pointer rewind (REW) When the the specified pipe is receiving, if "1" is written to this bit during the FIFO buffer read, the initial data of the FIFO buffer can be read (for a double buffer, the initial data on one side can be read again during the read process). When the software writes "1" to this bit, the controller again writes "0" to this bit. Do not modify the "REW=1" and CURPIPE bit settings at the same time. First confirm that "FRDY=1" and then write "REW=1". Use the BLCR bit while rewriting the initial data of the FIFO buffer for the transmission pipe. 2.8.5 CFIFO Port access bit width (MBW) In this bit, set the CFIFO port access bit width. When the pipe specified in the CURPIPE bit is receiving, if read is started after writing "1" to this bit, modify the MBW bit from "1" to "0" only after all the data is read. When the DTLN bit is an odd number, write "MBW=0" and read with the variable having an 8-bit length, or read with a 16-bit maintaining "MBW=1", delete the excess byte, and then read the last byte. When the specified pipe is receiving, set the CURPIPE bit and MBW bit simultaneously. When the the specified pipe is transmitting, to start writing the data having an odd number of bytes by writing "1" to this bit, write "MBW=0" and write with the variable having a 16-bit length (refer to 2.8.2 for the data to be written), or write with the variable having an 8-bit length maintaining "MBW=1", and then write the last byte (write with the WR0_N strobe if "BIGEND=0", and with the WR1_N strobe if "BIGEND=1"). 2.8.6 Control bit of CFIFO port byte endian (BIGEND) In this bit, write the CFIFO port byte endian. Refer to 2.8.2 for details. 2.8.7 FIFO port access direction specification bit when selecting DCP (ISEL) To change this bit when the specified pipe is DCP, first write the data to this bit and then read it. Proceed to the next process after checking if the written values match with the read values. When the settings of this bit are modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be continued after rewriting the settings. Write to this bit and the CURPIPE bit simultaneously. 2.8.8 FIFO port access byte specification bit (CURPIPE) Write the pipe number for the data to be read or written through the CFIFO port. When modifying this bit, first write the data and then read it. Check that the written values and the read values match, and then proceed to the next process. Do not write to the same pipe to CURPIPE of CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers. When the settings of this bit are modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be continued after rewriting the settings. Rev1.01 Oct 17, 2008 page 42 of 183 R8A66597FP/DFP/BG D0FIFO port selection register [D0FIFOSEL] D1FIFO port selection register [D1FIFOSEL] 15 14 13 12 11 10 RCNT REW DCLRM DREQE MBW 0 0 0 0 ? 0 ? Bit Name 9 ? ? 8 BIGEND 0 - 7 ? ? 6 ? ? 5 ? ? 4 ? ? 3 ? ? Function Software Hardware Remarks Specify the read mode of Dx_FIFOCTR DTLN. 0: The DTLN bit is cleared when all the reception data has RCNT 15 been read R/W R Read count mode 1: The DTLN bit is decremented when the reception data is read Specify "1" to rewind the buffer pointer. REW 0: Invalid R(0)/W R/W(0) 14 Buffer pointer rewind 1: The buffer pointer is rewound DCLRM Specify whether auto buffer memory clear is This is the auto buffer memory disabled/enabled after the data for the specified pipe has 13 clear mode accessed after the been read. R/W R data for the specified pipe has 0: Auto buffer clear mode is disabled been read. 1: Auto buffer clear mode is enabled Specify whether the DREQ signal is disabled/enabled. DREQE 0: Output is disabled 12 R/W R DREQ signal output enabled 1: Output is enabled 11 Unassigned. Fix to "0". Specify the FIFO port access bit width. MBW 0: 8-bit width 10 R/W R FIFO port access bit width 1: 16-bit width 9 Nothing is assigned. Fix to "0". Specify the byte endian of each FIFO port. BIGEND 0: Little endian R/W R 8 FIFO port endian control 1: Big endian 7-4 Unassigned. Fix to "0". 0000: No specification 0001: Pipe1 0010: Pipe2 1000: Pipe8 1001: Pipe9 CURPIPE 3-0 FIFO port access pipe specification R/W R Remarks None 2.8.9 Read count mode (RCNT) When "1" is written to this bit, if all reception data of the FIFO buffer assigned to the pipe specified in the CURPIPE bit is read (for a double buffer, when the data on one side is read), the controller clears the DxFIFOCTR register DTLN bit to "0". When "1" is written to this bit, the controller counts the DxFIFOCTR register DTLN bits each time during the reception data read of the FIFO buffer assigned to the specified pipe. Write "0" to this bit to access DxFIFO by writing "1" to the BFRE bit. Rev1.01 Oct 17, 2008 page 43 of 183 R8A66597FP/DFP/BG 2.8.10 Buffer pointer rewind (REW) When the specified pipe is receiving, if "1" is written to this bit during the FIFO buffer read, the read can be started from the initial data of the FIFO buffer (for a double buffer, during the read process, the initial data on one side can be read again). When the software writes "1" to this bit, the controller again writes "0" to this bit. Do not write "REW=1" and modify the CURPIPE bit. First check "FRDY=1" and then write "REW=1". While accessing DxFIFO by writing "1" to the BFRE bit, do not write "1" to this bit when the short packet data is read. Use the BLCR bit while rewriting the initial data of the FIFO buffer for the transmission pipe. 2.8.11 Auto FIFO buffer clear disabled/enabled bit (DCLRM) After reading the specified pipe data, set disabled/enabled for the auto FIFO buffer clear. When "1" is written to this bit, the controller executes a "BCLR=1" process of the FIFO buffer if a zero-length packet is received when the FIFO buffer assigned to the specified pipe is empty, or when the short packet reception data is read if writing "BFRE=1". If "BRDYM=1" is written when using this controller, make sure to write "0" to this bit. 2.8.12 DREQx_N output disabled/enabled bit (DREQE) Write this bit so that the DxREQ_N signal output can be disabled/enabled. When the DxREQ_N signal output is enabled, write "1" to this bit after writing to the CURPIPE bit. Write "0" to this bit and then modify the CURPIPE bit. 2.8.13 DxFIFO port access bit width (MBW) Write the DxFIFO port access bit width in this bit. Refer to 2.8.5 for details. 2.8.14 Control bit of DxFIFO port byte endian (BIGEND) Write the DxFIFO port byte endian in this bit. Refer to 2.8.2 for details. 2.8.15 FIFO port access pipe specification bit (CURPIPE) Write the pipe number for the data to be read or written through the DxFIFO port. To modify this bit, first write the data to this bit and then read it. Check if the write value matches the read value and then proceed to the next process. Do not write the same pipe to the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers' CURPIPE. When this bit is modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be continued after rewriting. Rev1.01 Oct 17, 2008 page 44 of 183 R8A66597FP/DFP/BG CFIFO port control register [CFIFOCTR] D0FIFO port control register [D0FIFOCTR] D1FIFO port control register [D1FIFOCTR] 15 14 13 12 11 10 BVAL BCLR FRDY 0 0 0 ? 0 0 ? Bit Name 9 0 - 8 0 - 7 0 - 6 DTLN 0 - 5 0 - 4 0 - 3 0 - 2 0 - Function Software Hardware Remarks R/W BVAL 15 Buffer memory valid flag 14 BCLR CPU buffer clear FRDY FIFO port ready 13 Specify "1" when write of the FIFO buffer ends on the CPU side of pipe specified in CURPIPE. R/W(1) 0: Invalid 1: Writing ended Specify "1" to clear the FIFO buffer on the CPU side of the pipe. R(0)/W(1) 0: Invalid 1: Clears the CPU buffer memory Indicates whether the FIFO port can be accessed. R 0: FIFO port access disabled 1: FIFO port access enabled Displays reception data corresponding PIPE. length of FIFO buffer for R/W(0) W 12 Unassigned. Fix to "0". 11-0 DTLN Reception data length R W Remarks None 2.8.16 Buffer memory valid flag (BVAL) When the pipe specified in the CURPIPE bit is transmitting, write "1" to this bit in the cases below. The controller writes the FIFO buffer from the CPU side to the SIE side to make transmission possible. (1) To transmit the short packet, write "1" to this bit after the data is written. (2) To transmit a zero-Length packet, write "1" to this bit before writing the data to FIFO. (3) For the pipe in continuous transfer mode, write "1" to this bit after writing the maximum packet size in multiples of natural integers and data less than the buffer size. If the data of the maximum packet size is written for the pipe in continuous transfer mode, the controller writes "1" to this bit, sets the CPU FIFO buffer to the SIE side, and changes to transmission possible status. When the controller indicates "FRDY=1", write "1" to this bit. When the specified pipe is receiving, do not write "1" to this bit. Rev1.01 Oct 17, 2008 page 45 of 183 R8A66597FP/DFP/BG 2.8.17 CPU buffer clear bit (BCLR) If "1" is written to this bit, the controller clears the FIFO buffer on the CPU side from the FIFO buffers assigned to the specified pipe. When the setting of the FIFO buffer assigned to the specified pipe is a double buffer, the controller clears the FIFO buffer only on one side, though the buffers on both sides can be read. When the specified pipe is DCP, the controller clears the FIFO buffer when "BCLR=1", irrespective of the CPU or SIE side. To clear the buffer on the SIE side, write "BCLR=1" after writing "NAK" to the PID bit. When the specified pipe is transmitting, if "1" is written simultaneously to the BVAL and BCLR bits, the controller clears the data written previously and changes the status of the zero-length packet to transmission possible. If the specified pipe is not DCP, write "1" to this bit when the controller sets "FRDY=1". 2.8.18 FIFO port ready bit (FRDY) In this bit, the controller shows if access is possible to the FIFO port from the CPU (DMAC). In the following cases, the controller sets "FRDY=1", but cannot read the data from the FIFO port since the data is not available. In these cases, write "BCLR=1", clear the FIFO buffer, and then change the status to Data Send/Receive. (1) If a zero-length packet is received when the FIFO buffer assigned to the specified pipe is empty. (2) If "BFRE=1" is written, when the short packet is received and the data is read. 2.8.19 Reception data length bit (DTLN) The controller sets the reception data length in this bit. The value of this bit changes according to the setup value of the RCNT bit during the FIFO buffer read. (1) When "RCNT=0": The controller sets the reception data length in this bit until the CPU (DMAC) reads all the reception data on one side of the FIFO buffer. When "BFRE=1", the controller holds the reception data length until "BCLR=1", although the data is read. (2) When "RCNT=1": The controller counts the DTLN bit display during each data read (counts down by -1 when "MBW=0", and by -2 when "MBW=1"). When the data on one side of the FIFO buffer is read, the controller sets "DTLN=0". However, when the double buffer is set, and when data is received in the FIFO buffer on one side before reading the reception data on other FIFO buffer, the reception data on one side is set in the DTLN bit when read on the first side is being completed. When "RCNT=1", while reading the value of this bit during FIFO buffer read, the controller sets the updated value of this bit up to150ns after the read cycle of the FIFO port. Rev1.01 Oct 17, 2008 page 46 of 183 R8A66597FP/DFP/BG 2.9 Interrupts Enabled Interrupt enabled register 0 [INTENB0] 15 14 13 12 11 10 9 8 VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE 0 0 0 0 0 0 0 0 Bit Name 7 ? ? Function 6 ? ? 5 ? ? 4 ? ? 3 ? ? 2 ? ? Software Hardware while R/W while R/W while R/W while R/W while R/W while R/W while R/W while R/W R R R R R R R R VBSE 15 VBUS interrupts enabled 14 13 12 11 10 9 8 7-0 Specify INT_N disabled/enabled detecting VBINT interrupts. 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled RSME detecting RESM interrupt. Resume interrupts enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled SOFE detecting SOF interrupt. Frame number update interrupts 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled DVSE detecting DVST interrupt. Device state transition interrupts 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled CTRE detecting CTRT interrupt. Control transfer stage transition 0: Interrupt output disabled interrupts enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled BEMPE detecting BEMP interrupt. Buffer empty interrupts enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled NRDYE detecting NRDY interrupt. Buffer not ready response interrupts 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled BRDYE detecting BRDY interrupt. Buffer ready interrupts enabled 0: Interrupt output disabled 1: Interrupt output enabled Unassigned. Fix to "0". P (Write to "0" when H) P (Write to "0" when H) P (Write to "0" when H) Remarks * RESM, DVSE and CTRE bits can be written to only when the Peripheral Controller function is selected. Do not enable when the Host Controller function is selected. Rev1.01 Oct 17, 2008 page 47 of 183 R8A66597FP/DFP/BG Interrupt enabled register 1 [INTENB1] 15 14 13 12 11 OVRCRE BCHGE DTCHE ATTCHE 0 0 ? 0 0 ? Bit Name OVRCRE Port0 OVRCR interrupt enabled 10 ? ? 9 ? ? 8 ? ? 7 ? ? 6 5 4 EOFERRE SIGNE SACKE 0 0 0 - 3 ? ? 2 ? ? Function Software R/W Hardware R Specify INT_N assert disabled/enabled while detecting Port0 OVRCR interrupt. 15 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while BCHGE detecting Port0 BCHG interrupt. 14 Port0 USB bus change interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 13 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while DTCHE detecting Port0 DTCH interrupt (enabled only if 12 Port0 detach detect interrupt HOST). enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while ATTCHE detecting Port0 ATTCH interrupt. 11 Port0 attach detect interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 10-7 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while EOFERRE detecting Port0 EOFERR interrupt. 6 Port0 EOF error detect interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while SIGNE detecting Port0 SIGN interrupt. 5 Port0 Setup transaction error 0: Interrupt output disabled interrupt enabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while SACKE detecting Port0 SACK interrupt. 4 Port0 Setup transaction complete 0: Interrupt output disabled interrupt enabled 1: Interrupt output enabled 3-0 Unassigned. Fix to "0". R/W R R/W R H (Write to "0" when P) H (Write to "0" when P) H (Write to "0" when P)" H (Write to "0" when P)" H (Write to "0" when P)" R/W R R/W R R/W R R/W R Remarks * The interrupt enabled by the INTENB1 register except the OVRCRE bit can be written to only when the Host Controller function is selected. Do not enable it when the Peripheral Controller function is selected. * The interrupt enabled by the OVRCRE bit can be written to only when the Host Controller function is selected or operate the controller as an OTG A-Device. Rev1.01 Oct 17, 2008 page 48 of 183 R8A66597FP/DFP/BG Interrupt enabled register 2 [INTENB2] 15 14 13 12 11 OVRCRE BCHGE DTCHE ATTCHE 0 0 ? 0 0 ? Bit Name 10 ? ? 9 ? ? 8 ? ? 7 ? ? Function 6 EOFERRE 5 ? ? 4 ? ? 3 ? ? 2 ? ? 0 - Software Hardware Remarks R/W R H (Write to "0" when P)" H (Write to "0" when P)" Specify INT_N assert disabled/enabled while OVRCRE detecting Port1 OVRCR interrupt. 15 Port1 OVRCR interrupt enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while BCHGE detecting Port1 BCHG interrupt. 14 Port1 USB bus change interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 13 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while detecting Port1 DTCH interrupt (enabled only if DTCHE 12 HOST). Port1 detach detect interrupt enabled 0: Interrupt output disabled 1: Interrupt output enabled Specify INT_N assert disabled/enabled while ATTCHE detecting Port1 ATTCH interrupt. 11 Port1 attach detect interrupt enabled 0: Interrupt output disabled 1: Interrupt output enabled 10-7 Unassigned. Fix to "0". Specify INT_N assert disabled/enabled while EOFERRE detecting Port1 EOFERR interrupt. 6 Port1 EOF error detect interrupt 0: Interrupt output disabled enabled 1: Interrupt output enabled 5-0 Unassigned. Fix to "0". R/W R R/W R H (Write to "0" when P)" H (Write to "0" when P)" H (Write to "0" when P)" R/W R R/W R Remarks * The interrupt enabled by the INTENB2 register can be written to only when the Host Controller function is selected. Do not enable it when the Peripheral Controller function is selected. 2.9.1 Interrupt enabled registers 0, 1, 2 (INTENB0, INTENB1, INTENB2) When the controller detects the interrupt corresponding to the bit for which the software has written "1" to the register, the controller asserts an interrupt from the INT_N pin. The controller sets "1" to this status bit corresponding to the INTSTS0, INTSTS1 and INTSTS2 registers when the detection conditions of each interrupt factor are satisfied, irrespective of the setup value of the register (interrupt notification disabled/enabled). When the status bit of the INTSTS0, INTSTS1 and INTSTS2 registers corresponding to each interrupt factor are set to "1", if the software modifies the interrupt enabled bit corresponding to the register from "0" to "1", the controller asserts the interrupt from the INT_N pin. Rev1.01 Oct 17, 2008 page 49 of 183 R8A66597FP/DFP/BG BRDY interrupt enabled register [BRDYENB] 15 14 13 12 11 10 ? ? Bit ? ? ? ? ? ? Name ? ? ? ? 9 0 - 8 0 - 7 0 Function 6 0 - 5 4 PIPEBRDYE 0 0 - 3 0 - 2 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". PIPEBRDYE 9-0 Interrupts for enabled each pipe Specify whether it is possible to write "1" to the BRDY bit while detecting the BRDY bit of each pipe. are 0: Interrupt output disabled 1: Interrupt output enabled R/W R Remarks * The bit number corresponds to the pipe number. 2.9.2 BRDY interrupt enabled bit of each pipe (PIPEBRDYE) When the controller detects the BRDY interrupt for the pipe for which the software has written "1" in this bit, it sets "1" to the BRDYSTS register PIPEBRDY bit and to the INTSTS0 register BRDY bit, and asserts an interrupt from the INT_N pin. When at least one bit from the BRDYSTS register PIPEBRDY bit sets "1", if the software modifies the register interrupt enabled bit from "0" to "1", the controller asserts an interrupt from the INT_N pin. NRDY interrupt enabled register [NRDYENB] 15 14 13 12 11 10 ? ? Bit ? ? ? ? ? ? Name ? ? ? ? 9 0 - 8 0 - 7 0 Function 6 0 - 5 4 PIPENRDYE 0 0 - 3 0 - 2 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". Specify whether it is possible to write "1" to the NRDY PIPENRDYE bit while detecting the BRDY interrupt of each pipe. 9-0 NRDY interrupt for each pipe is 0: Interrupt output disabled enabled 1: Interrupt output enabled Remarks * Bit number corresponds to the pipe number. R/W R 2.9.3 NRDY interrupt enabled bit of each pipe (PIPENRDYE) When the controller detects the NRDY interrupt for the pipe for which the software has written "1" to this bit, it sets "1" to the NRDYSTS register PIPEBRDY bit and to the INTSTS0 register NRDY bit, and asserts an interrupt from the INT_N pin. When at least one bit from the NRDYSTS register PIPENRDY bit sets "1", if the software modifies the interrupt enabled bit of the register from "0" to "1", the controller asserts an interrupt from the INT_N pin. Rev1.01 Oct 17, 2008 page 50 of 183 R8A66597FP/DFP/BG BEMP interrupt enabled register [BEMPENB] 15 14 13 12 11 10 ? ? Bit ? ? ? ? Name ? ? ? ? ? ? 9 0 - 8 0 - 7 0 Function 6 0 - 5 4 PIPEBEMPE 0 0 - 3 0 - 2 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". 9-0 Specify whether it is possible to write "1" to the BEMP PIPEBEMPE bit while detecting the BEMP interrupt of each pipe. BEMP interrupt for each pipe is 0: Interrupt output disabled enabled 1: Interrupt output enabled R/W R Remarks * Bit number corresponds to the pipe number. 2.9.4 BEMP interrupt enabled bit of each pipe (PIPEBEMPE) When the controller detects the BEMP interrupt for the pipe for which the software has written "1" to this bit, it sets "1" to the PIPEBEMP register PIPEBEMP bit and to the INTSTS0 register BEMP bit, and asserts an interrupt from the INT_N pin. When at least one bit from the BEMPSTS register PIPEBEMP bit sets "1", if the software modifies the register interrupt enabled bit from "0" to "1", the controller asserts an interrupt from the INT_N pin. Rev1.01 Oct 17, 2008 page 51 of 183 R8A66597FP/DFP/BG 2.10 SOF Control Register SOF pin configuration register [SOFCFG] 15 14 13 12 11 10 ? ? Bit ? ? ? ? ? ? Name ? ? ? ? 9 ? ? 8 TRNENSEL 7 ? ? 0 - 5 4 BRDYM INTL EDGESTS 0 0 0 - 6 3 2 SOFM 0 0 - Function This controller specifies the time period (transaction validity) for issuing the token within one frame for the port during Full-/Low-Speed communication. 0: Not compatible with Low-Speed 1: Compatible with Low-Speed Software Hardware Remarks 15-9 Unassigned. Fix to "0". TRNENSEL 8 Transaction validity switchover bit 7 Unassigned. Fix to "0". BRDYM 6 PIPEBRDY interrupt timing setting Specify the timing for clearing the PIPEBRDY interrupt status. 0: Software clears the status clear 1: Hardware clears the status by read operation of the FIFO buffer or by write operation to the FIFO buffer Specify interrupt output sense of the INT_N pin. 0: Edge sense 1: Level sense Interrupt edge process status is set. 0: Interrupt edge non-active 1: Interrupt edge active Select SOF pulse output mode. 00: SOF output disabled 01: SOF output in 1ms unit 10: SOF output in 125s unit 11: Reserved H (Write to "0" when P) R/W R status R/W R 5 INTL Interrupt output sense setting EDGESTS Interrupt edge process status R/W R 4 R/W R 3-2 SOFM SOF pin settings R/W R 1-0 Unassigned. Fix to "0". Remarks * Writing to the TRNENSEL bit is valid only when the Host Controller function is selected. The transaction validity of Hi-Speed is not affected, although the Host Controller function is selected. This bit is common for two ports. * While writing "BRDYM=1", write "INTL=1" (level sense). * While writing "INTL=0", clear interrupt status, confirm "EDGESTS=0" to stop the system clock (write "SCKE=0") and then write "SCKE=0". Rev1.01 Oct 17, 2008 page 52 of 183 R8A66597FP/DFP/BG 2.11 Interrupt Statuses Interrupt status register 0 [INTSTS0] 15 14 13 12 11 10 9 8 7 VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS 0 0 0 0 0 0 0 0 ? 1 Bit 15 Name VBINT VBUS change detect interrupt status 6 0 0 5 DVSQ 0 0 4 0 1 3 VALID 0 - 2 0 - Function VBUS change detection interrupt status is set. 0: VBUS interrupts not issued 1: VBUS interrupts issued Resume detection interrupt status is set. 0: Resume interrupts not issued 1: Resume interrupts issued Frame number refresh interrupt status is set. 0: SOF interrupts not issued 1: SOF interrupts issued Device state transition interrupt status is set. Status 0: Device state transition interrupts not issued 1: Device state transition interrupts issued Software Hardware Remarks R/W(0) W P (Read value invalid when H) 14 RESM Resume interrupt status R/W(0) W 13 SOFR Frame number update interrupt status R/W(0) W P (Read value invalid when H) P (Read value invalid when H) DVST 12 Device state transition interrupt status R/W(0) W Control transfer stage transition interrupt status is set. CTRT Status 11 Control transfer stage transition interrupt 0: Control transfer stage transition interrupts not status issued 1: Control transfer stage transition interrupts issued BEMP interrupt status is set. BEMP 10 0: BEMP interrupts not issued BEMP interrupt status 1: BEMP interrupts issued NRDY interrupt status is set. NRDY 9 0: NRDY interrupts not issued NRDY interrupt status 1: NRDY interrupts issued BRDY interrupt status is set. BRDY 8 0: BRDY interrupts not issued BRDY interrupt status 1: BRDY interrupts issued Input status of VBUS pin is set. VBSTS 7 0: VBUS pin is "L" level VBUS input status 1: VBUS pin is "H" level Device state is set. 000: Powered state DVSQ 001: Default state 6-4 Device state 010: Address state 011: Configured state 1xx: Suspended state VALID USB request reception USB request reception detection valid/invalid is set. 0: Not detected 1: Setup packet reception R/W(0) W R W R W R W R W P (Read value invalid when H) P (Read value invalid when H) R W 3 R/W(0) W Rev1.01 Oct 17, 2008 page 53 of 183 R8A66597FP/DFP/BG Bit Name Function Control transfer stage is set. 000: Idle or Setup stage 001: Control read data stage 010: Control read status stage 011: Control write data stage 100: Control write status stage 101: Control write (no data) status stage 110: Control transfer sequence error 111: Reserved Software Hardware Remarks 2-0 CTSQ Control transfer stage R W P (Read value invalid when H) Remarks * To clear the status indicated by the VBINT, RESM, SOFR, DVST or CTRT bits, write "0" only for the bit to be cleared, and write "1" for other bits. Do not write "0" to the status bit set to "0". * The controller detects the change in status indicated by the VBINT and RESM bits of this register, even while the clock is being stopped ("SCKE=0"), and notifies the interrupt if the corresponding interrupt is enabled. When the clock is enabled, clear the status using software. * The statuses of the RESM, DVST and CTRT bits change only when the Peripheral Controller function is selected. When the Host Controller function is selected, write "0" to the corresponding interrupt enabled bit in order to disablethe the interrupt. * The DVSQ, VALID and CTRQ bits are valid only when the Peripheral Controller function is selected. 2.11.1 VBUS conversion interrupt status bit (VBINT) When the controller detects the change in the VBUS pin input value (from High to Low and from Low to High), "1" is written to this bit. The controller writes the input value of the VBUS pin to the VBSTS bit. When the VBINT interrupt occurs, use the software to execute a consistency check several times during the VBSTS bit read, and reject the chattering. 2.11.2 Resume interrupt status bit (RESM) When writing to the Peripheral Controller function, the controller is in suspend status (DVSQ=1XX), and "1" is set to this bit when the DP pin falling edge is detected. 2.11.3 Frame number update interrupt status bit (SOFR) The conditions when the controller sets "1" in this bit are below. 2.11.3.1 When the Host Controller function is set This controller sets "1" for this bit in the condition where at least one of the UACT bits corresponding to Port0 or Port1 writes "1" by the software, during the timing when the frame number is updated (this interrupt is detected every 1ms). 2.11.3.2 When the Peripheral Controller function is set While updating the frame number, the controller sets "1" to this bit (this interrupt is detected every 1ms). The controller detects the SOFR interrupt by internal interpolation even if the SOF packet from the USB Host is corrupted. 2.11.4 Device state transition interrupt status bit (DVST) When the Peripheral Controller function is set, if the controller detects a change in the device state, it updates the DVSQ value and sets "1" to this bit. When this interrupt occurs, clear the status before the controller detects the next device status state transition. Rev1.01 Oct 17, 2008 page 54 of 183 R8A66597FP/DFP/BG 2.11.5 Control transfer and stage transition interrupt status bit (CTRT) When writing the Peripheral Controller function, if the controller detects the stage transition of control transfer, it updates the CTSQ value and sets "1" to this bit. When this interrupt occurs, clear the status before the controller detects stage transition after the control transfer. 2.11.6 Buffer empty interrupt status bit (BEMP) The controller sets "1' in the interrupt when, among the BEMPSTS register PIPEBEMP bits corresponding to the pipe for which "1" is written to the BEMPENB register PIPEBEMPE bit (when the controller detects the BEMP interrupt status for at least one pipe from the pipes for which the software has enabled the BEMP interrupt notification), at least one bit is "1". Refer to the PIPEBEMP register for assert conditions of the PIPEBEMP status. If the software writes "0" for all the PIPEBEMP bits corresponding to the pipe that is enabled by the PIPEBEMPE bit, the controller clears this bit to "0'. This bit cannot be cleared to "0" even if "0" is written to this bit by the software. 2.11.7 Buffer not ready interrupt status bit (NRDY) The controller sets "1" in the interrupt when, among the BNRDYSTS register PIPENRDY bits corresponding to the pipe for which "1" is written to the NRDYENB register PIPENRDYE bit (when the controller detects the NRDY interrupt status for at least one pipe from the pipes for which the software has enabled the NRDY interrupt notification), at least one bit is "1". Refer to the PIPENRDY register for assert conditions of the PIPENRDY status. If the software writes "0" to all the PIPENRDY bits corresponding to the pipe that is enabled by the PIPENRDYE bit, the controller clears this bit to "0". This bit cannot be cleared to "0' even if the software writes "0" to this bit. 2.11.8 Buffer ready interrupt status bit (BRDY) The controller sets "1" in the interrupt when, among the BRDYSTS register PIPEBRDY bits corresponding to the pipe for which "1" is written in the BRDYENB register PIPEBRDYE bit (when the controller detects the BRDY interrupt status for at least one pipe from the pipes for which the software has enabled the BRDY interrupt notification), at least one bit is "1". Refer to the PIPEBRDY register for the assert conditions of the PIPEBRDY status. If the software writes "0" to all the PIPEBRDY bits corresponding to the pipe that is enabled by the PIPEBRDYE bit, the controller clears this bit to "0". This bit cannot be cleared to "0" even if the software writes "0" to this bit. Rev1.01 Oct 17, 2008 page 55 of 183 R8A66597FP/DFP/BG Interrupt status register 1 [INTSTS1] 15 14 13 12 11 OVRCR BCHG DTCH ATTCH 0 0 ? 0 0 ? Bit Name OVRCR Port0 OVRCR interrupt status 10 ? ? 9 ? ? 8 ? ? 7 ? ? 6 5 4 EOFERR SIGN SACK 0 0 0 - 3 ? ? 2 ? ? Function Software Hardware Remarks H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) 15 Port0 OVRCR interrupt status is set. This interrupt is issued when the input status of OVCUR0A pin or OVCUR0B pin is modified. R/W(0) 0: OVRCR interrupt not issued 1: OVRCR interrupt issued W 14 BCHG Port0 USB bus change interrupt status is set. Port0 USB bus modify interrupt 0: BCHG interrupt not issued status 1: BCHG interrupt issued Unassigned. Fix to "0". DTCH Port0 USB detach detect interrupt status Port0 USB detach detect interrupt status is set. 0: DTCH interrupt not issued 1: DTCH interrupt issued R/W(0) W 13 12 R/W(0) W 11 ATTCH Port0 ATTCH interrupt status is set. Port0 USB attach detect interrupt 0: ATTCH interrupt not issued status 1: ATTCH interrupt issued R/W(0) W 10-7 Unassigned. Fix to "0". EOFERR Port0 EOFERR interrupt status is set. Port0 EOF error detect interrupt 0: EOFERR interrupt not issued status 1: EOFERR interrupt issued 6 R/W(0) W 5 SIGN Setup transaction error interrupt status is set. Setup transaction error interrupt 0: SIGN interrupt not issued status 1: SIGN interrupt issued R/W(0) W 4 Setup transaction normal response interrupt status is SACK set. Setup transaction normal R/W(0) 0: SACK interrupt not issued response interrupt status 1: SACK interrupt issued W 3-0 Unassigned. Fix to "0". Remarks * Enable the interrupt caused by the status changes indicated by each bit of this register, only when the Host Controller function is selected. * To clear the status of each bit of this register, use the software to write "0" only to the bit which is to be cleared, and "1" to other bits. * The controller detects the change in status indicated by the OVRCR and BCHG bits of this register even while the clock is being stopped ("SCKE=0"), and notifies the interrupt if the corresponding interrupt is enabled. When the clock is enabled, use the software to clear the status. Interrupt for bits other than the OVRCR and BCHG bits cannot be detected while the clock is being stopped ("SCKE=0"). Rev1.01 Oct 17, 2008 page 56 of 183 R8A66597FP/DFP/BG 2.11.9 Port0 OVRCR Interrupt status bit (OVRCR) When input status of the OVCUR0A or OVCUR0B pin is modified (from Low to High, or from High to Low), this controller detects the Port0 OVRCR interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This controller shows the present input status for the OVCUR0A and OVCUR0B pins in the SYSSTS0 register OVCMON bit. When selecting the Host Controller function, it is possible to detect the occurrence of the software over-current if the over-current notification signal from the power supply IC, which supplies the VBUS for the devices to be connected to the USB on Port0, is written to the OVCUR0A or OVCUR0B pin. When the OVRCR interrupt is issued, use the software several times to check the consistency in read of the OVCMON bit and reject the chattering. 2.11.10 Port0 USB bus change interrupt status bit (BCHG) When a state change for Full-/Low-Speed signal level of Port0 is issued (modify from J-State, K-State, or SE0 State to J-State, K-State or SE0 State), this controller detects the Port0 BCHG interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This controller displays the present input status of Port0 in the SYSSTS0 register LNST bit. Enable the BCHG interrupt under the following conditions: (1) When enabling remote wakeup to enter the suspend status (2) When stopping the clock to enter the suspend status (necessary in order to detect detach during suspend status) (3) . When clock is stopped because no Peripheral Devices is connected (necessary to detect attach) When a BCHG interrupt occurs in condition (1), confirm the remote wakeup of the Peripheral Device with the DVSTCTR register RESUME bit. When a BCHG interrupt occurs under conditions (2) or (3), eliminate chattering on the LNST bit with software, and check for attach/detach to/from the Peripheral Device. 2.11.11 Port0 USB detach detection interrupt status bit for the Host Controller function (DTCH) When the USB bus detach for Port0 is detected, this controller detects the Port0 DTCH interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This controller detects the bus detach using the standards as given in the USB Specification Revision 2.0. This controller controls the hardware given below after detecting the DTCH interrupt (irrespective of the setting value of the applicable interrupt permitted bit). The software closes all communication by the pipe for all applicable ports. Then, modify the status to attach wait (issue ATTCH interrupt) for the applicable ports. (1) Modify the UACT bit of the port where the DTCH interrupt has been detected to "0" and set. (2) Modify the status of the port where the DTCH interrupt was issued to "idle". 2.11.12 Port0 USB attach detection interrupt status bit for the Host Controller function (ATTCH) When selecting the Host Controller function, and when this controller detects the J-State or K-State of Full-/Low-Speed signal level on Port0 within 2.5s, it detects the Port0 ATTCH interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. The specific ATTCH interrupt detection conditions for this controller are given below: (1) When modified from K-State, SE0 or SE1 to J-State and continued in the J-State for 2.5s (2) When modified from J-State, SE0 or SE1 to K-State and continued in the K-State for 2.5s Rev1.01 Oct 17, 2008 page 57 of 183 R8A66597FP/DFP/BG 2.11.13 Port0 EOF error interrupt status bit for the Host Controller function (EOFERR) When this controller detects that communication for Port0 is not closed at the point of EOF2 timing as defined in the USB Specification Revision 2.0, it detects the Port0 EOFERR interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is generated. This controller controls the hardware shown below after detecting the EOFERR interrupt (regardless of the written value to the applicable interrupt permitted bit). The software closes all communication by the pipe for all applicable ports. Then, re-enumerate the applicable ports. (1) Modify the port UACT bit where the EOFERR interrupt has been detected to "0" and set. (2) Modify the status of the port where the EOFERR interrupt was issued to "idle". 2.11.14 Setup transaction error interrupt status bit for the Host Controller function (SIGN) When the Setup transaction is issued by this controller, and is issued three times consecutively, in the state where no ACK response is received from the Peripheral device, this controller detects the Port0 SIGN interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is generated. The specific SIGN interrupt detection conditions for this controller when one of the three responses given below are received for the Setup transaction issued three times consecutively: (1) When a timeout is detected in the state when the Peripheral device does not respond (2) When the ACK packet is corrupt (3) When a handshake (NAK, NYET, or STALL) other than ACK is received 2.11.15 Setup transaction normal acknowledgement interrupt status bit for the Host Controller function (SACK) When the Setup transaction is issued by this controller and the ACK response is received from the Peripheral device, this controller detects the Port0 SACK interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is generated. Rev1.01 Oct 17, 2008 page 58 of 183 R8A66597FP/DFP/BG Interrupt status register 2 [INTSTS2] 15 14 13 12 11 OVRCR BCHG DTCH ATTCH 0 0 ? 0 0 ? Bit Name OVRCR Port1 OVRCR interrupt status 10 ? ? 9 ? ? 8 ? ? 7 ? ? 6 EOFERR 0 - 5 ? ? 4 ? ? 3 ? ? 2 ? ? Function Software Hardware Remarks H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) H (Read value invalid when P) 15 Port1 OVRCR interrupt status is set. When the input status of the OVCUR1 pin is modified, this interrupt is issued. R/W(0) 0: OVRCR interrupt not issued 1: OVRCR interrupt issued W BCHG Port1 USB bus modify interrupt status is set. 14 Port1 USB bus modify interrupt 0: BCHGinterrupt not issued status 1: BCHGinterrupt issued 13 Unassigned. Fix to "0". DTCH 12 Port1 detach status Port1 detach detect interrupt status is set. interrupt 0: DTCHinterrupt not issued 1: DTCHinterrupt issued R/W(0) W detect R/W(0) W ATTCH 11 Port1 attach status detect Port1 ATTCH interrupt status is set. interrupt 0: ATTCH interrupt not issued 1: ATTCH interrupt issued R/W(0) W 10-7 Unassigned. Fix to "0". EOFERR Port1 EOFERR interrupt status is set. Port1 EOF error detect interrupt 0: EOFERR interrupt not issued status 1: EOFERR interrupt issued 6 R/W(0) R 5-0 Unassigned. Fix to "0". Remarks * Enable the interrupt caused by the changes in status shown by each bit of the register, only when the Host Controller function is selected. * To clear the status of each bit of this register, use the software to write "0" only to the bit which is to be cleared, and "1" to the other bits. * The controller detects the change in status indicated by the OVRCR and BCHG bits of this register, even while the clock is being stopped ("SCKE=0"), and notifies the interrupt if the corresponding interrupt is enabled. When the clock is enabled, use the software to clear the status. Interrupt for the bits other than the OVRCR and BCHG bits cannot be detected while the clock is being stopped ("SCKE=0"). Rev1.01 Oct 17, 2008 page 59 of 183 R8A66597FP/DFP/BG 2.11.16 Port1 OVRCR interrupt status bit (OVRCR) When input status of the OVCUR1 pin is modified (from High to Low, or from Low to High), this controller detects the Port1 OVRCR interrupt and setss "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This controller shows the present status of the OVCUR1 pin in the SYSSTS1 register OVCMON bit. When selecting the Host Controller function, it is possible to detect the software over-current occurrence if the over-current notification signal from the power supply IC that supplies to the VBUS for the devices to be connected to the USB on Port1 is set to the OVCUR1 pin. When the OVRCR interrupt is issued, use the software to check the consistency in reading of OVCMON bit several times and reject the chattering. 2.11.17 Port1 USB bus change interrupt status bit (BCHG) When a state change for the Port1 Full-/Low-Speed signal level is issued (from J-State, K-State, or SE0 State to J-State, K-State or SE0 State), this controller detects the Port1 BCHG interrupts and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This controller displays the present input status of Port0 in the SYSSTS1 register LNST bit. Refer to 2.11.10. 2.11.18 Port1 USB detach detection interrupt status bit for the Host Controller function (DTCH) When the USB bus detach for Port1 is detected, this controller detects the Port1 DTCH interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. Refer to 2.11.11. 2.11.19 Port1 USB attach detection interrupt status bit for the Host Controller function (ATTCH) When selecting the Host Controller function, and when this controller detects the J-State or K-State of the Full-/Low-Speed signal level on Port0 within 2.5s, this controller detects the Port1 ATTCH interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. Refer to 2.11.12. 2.11.20 Port1 EOF error interrupt status bit for the Host Controller function (EOFERR) When this controller detects that the communication for Port1 is not closed at the point of EOF2 timing as defined in the USB Specification Revision 2.0, this controller detects the Port1 EOFERR interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. Refer to 2.11.13. Rev1.01 Oct 17, 2008 page 60 of 183 R8A66597FP/DFP/BG BRDY interrupt status register [BRDYSTS] 15 14 13 12 11 10 ? ? Bit ? ? ? ? ? ? Name ? ? ? ? 9 0 - 8 0 - 7 0 Function 6 0 - 5 4 PIPEBRDY 0 0 - 3 0 - 2 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". 9-0 PIPEBRDY BRDY interrupt status of each pipe BRDY interrupt status of each pipe is set. 0: Interrupt not issued 1: Interrupt issued R/W(0) W Remarks * Bit number corresponds to the pipe number. * If writing "BRDYM=0", to clear the status of each bit of this register, write "0" only to the bit that is to be cleared and "1" to other bits. * If writing "BRDYM=0", clear this interrupt before accessing the FIFO. 2.11.21 BRDY interrupt status bit of each pipe (PIPEBRDY) When the BRDY interrupt is detected for the pipe with the controller, the controller sets "1" in the BRDYSTS register PIPEBRDY bit. Here, by using the software when "1" is written to the bit corresponding to BRDYENB register, the controller sets "1" to the INTSTS0 register BDY bit and asserts the interrupt from the INT_N pin. For the BRDY interrupt, occurrence conditions and clearing method change according to the BRDYM and BFRE bits of each pipe. 2.11.21.1 Writing "BRDYM=0" and "BFRE=0" For these, the BRDY interrupt indicates the possibility of access to the FIFO port. In the following conditions, the controller issues the internal BRDY interrupt request trigger and sets "1" in the PIPEBRDY bit corresponding to the pipe for which a request trigger was issued. (1) When the pipe is set to transmit (a) When the software has modified the DIR bit from "0" to "1". (b) When the controller ends the packet transmission of the pipe in the condition where write is not possible from the CPU to the FIFO buffer that has been assigned to the pipe (when the BSTS bit read value is "0"). When set to continuous transmission/reception, the request trigger is issued when transmission of one FIFO buffer is complete. (c) When the FIFO buffer is set to double buffer, one side of the FIFO buffer is empty even if writing to other side is completed. During writing to the FIFO buffer, the request trigger is not issued until write on other side is completed, even if write on one side is completed. (d) In an isochronous transfer type pipe, when the hardware causes a buffer flash. (e) When the status of the FIFO bit has been modified from "write disabled" to "write enabled" by writing "1" to the ACLRM bit. Request trigger is not issued for DCP (in other words, in data transmission of control transfer). (2) When the pipe is set to receive (a) When the controller ends the packet transmission of the pipe in the condition where write is not possible from the CPU to the FIFO buffer that has been assigned to the pipe (when the BSTS bit read value is "0"). A request trigger is not issued for the transaction of data PID mismatch. When set to continuous transmission/reception mode, the request trigger is issued when transmission of one FIFO buffer is complete. When a short packet is received, the request trigger is issued even if space is available in the FIFO buffer. While using the transaction counter, a request trigger is issued when a packet of setup value is received. Here, the request trigger is issued even if space is available in the FIFO buffer. (b) When the FIFO buffer is set to double buffer, if the FIFO buffer read is complete, one more FIFO buffer read becomes possible. If one more buffer is received during read, the request trigger is not issued until the read of the current buffer is completed. When the Peripheral Controller function is selected, this interrupt is not issued during communication with the control Rev1.01 Oct 17, 2008 page 61 of 183 R8A66597FP/DFP/BG transfer status stage. The software can write to (clear) the PIPEBRDY interrupt status of the pipe to "0" by writing "0" to the bit corresponding to the pipe of this bit. Here, write "0" to the bits corresponding to other pipes. Clear the interrupt status before accessing the FIFO buffer. 2.11.21.2 Writing "BRDYM=0" and "BFRE=1" If writing these, when the controller reads all the data of one transfer in reception pipe, it is determined that a BRDY interrupt was issued and "1" is set in the bit corresponding to the pipe of register. In either of the following conditions, it is determined that the controller receives the final data in one transfer: (1) When a short packet, including a zero-length packet, is received (2) When a packet of TRNCNT bit setup value is received by using transaction counter (TRNCNT bit) When this data is read after fulfilling the above-mentioned determination conditions, the controller concludes that the entire data of one transfer is read. If a zero-length packet is received when the FIFO buffer is empty, the controller concludes that the entire data of one transfer is read when a zero-length packet on CPU side is toggled. In this case, to start the next transfer by using the software, write "1" to the BCLR bit of corresponding FIFOCTR register. If writing these, the controller does not detect BRDY interrupt for the transmission pipe. The software can write to (clear) the PIPEBRDY interrupt status of the pipe to "0" by writing "0" to the bit corresponding to the pipe of this bit , and by writing "1" to the bit corresponding to other pipe. While using this mode, do not modify the setup value of BFRE bit until the transfer process is completed. While modifying BFRE bit during the process, clear all the FIFO buffers of the corresponding pipe by ACLRM bit. 2.11.21.3 Writing "BRDYM=1" and "BFRE=0" If writing these, the bit value is coupled with the pipe's BSTS bit. In other words, the controller sets "1" or "0" depending on the FIFO buffer status of BRDY interrupt status. (1) When the pipe is set to transmit. Sets "1" when the data can be written in the FIFO port, otherwise sets "0". However, the BRDY interrupt is not asserted even if the DCP transmission pipe can be written to. (2) When the pipe is set to receive. Sets "1" when the data can be written in the FIFO port, and "0" when all the data is read (status changed to "Read disabled" status). When the FIFO buffer is empty and a zero-length packet is received, "1" is set in the corresponding bit until the software writes "BCLR=1", and the BRDY interrupt is asserted." If writing these, the software cannot write "0" to this bit. If writing "BRDYM=1", write "0" to all the BFRE bits (all pipes). If writing "BRDYM=1", write "1" to the INTL bit (level control). Rev1.01 Oct 17, 2008 page 62 of 183 R8A66597FP/DFP/BG NRDY Interrupt status register [NRDYSTS] 15 14 13 12 11 10 ? ? Bit ? ? ? ? ? ? Name ? ? ? ? 9 0 - 8 0 - 7 0 - 6 0 - 5 4 PIPENRDY 0 0 - 3 0 - 2 0 - Function NRDY interrupt status of each pipe is set. 0: Interrupt not issued 1: Interrupt issued Software Hardware Remarks 15-10 Unassigned. Fix to "0". 9-0 PIPENRDY NRDY interrupt status of each pipe R/W(0) W(1) Remarks * Bit number corresponds to the pipe number. * To clear the status indicated by each bit of the register, write "0"only the bit to be cleared and other bits to "1". 2.11.22 NRDY interrupt status bit of each pipe (PIPENRDY) For the pipe set to "PID=BUF" by the software, when the internal NRDY interrupt request is issued by the controller, it sets "1" to the bit corresponding to the NRDYSTS register PIPENRDY bit. Here, when the software is used to write "1" to the bit corresponding to the NRDYENB register, the controller sets "1" in the INTSTS0 register NRDY bit and asserts the interrupt from the INT_N pin. Conditions for the internal NRDY interrupt request for the pipe that is issued by the controller are given in 2.11.22.1, 2.11.22.2 and 2.11.22.3. However, while executing the Setup transaction when the Host Controller function is selected, the above-mentioned conditions do not correspond to the conditions for issuing the interrupt. When the Host Controller function is selected, a SACK interrupt or SIGN interrupt is detected in the Setup transaction. When the Peripheral Controller function is selected, an interrupt request is not issued while executing the control transfer status stage. Rev1.01 Oct 17, 2008 page 63 of 183 R8A66597FP/DFP/BG 2.11.22.1 If the Host Controller function is selected, and the connection where a split transaction does not occur (1) When the pipe is transmitting: When any of the conditions from (a) to (c) are fulfilled, the controller detects the NRDY interrupt. (a) In an isochronous transfer type pipe, when the time reaches the Out-token issue timing where transmission data does not exist in the FIFO buffer. Here, the controller sends a zero-length packet in continuation with the Out-token, sets "1" to the bit corresponding to the PIPENRDY bit, and also sets "1" to the OVRN bit. (b) In a transfer type pipe that is not isochronous, and in communications other than a Setup transaction, when a case occurs continuously three times in any combination where a Peripheral device is idle (no response) (detected timeout without detecting a handshake packet from the Peripheral device) or an error has been detected in the Peripheral device packet. Here, the controller sets "1" to the PIPENRDY bit and modifies the PID bit of the corresponding pipe to "NAK". (c) In communications other than a Setup transaction, when a stall handshake is received from the Peripheral device (STALL is related to OUT as well as PING). Here, the controller sets "1" to the bit corresponding to the PIPENRDY bit, and modifies the PID bit of corresponding pipe to "STALL(11)". (2) When the pipe is receiving: (a) In an isochronous transfer type pipe, the time reaches the In-token issue timing when there is no space in the FIFO buffer. Here, the controller deletes the reception data related to the In-token, sets "1" to the PIPENRDY bit corresponding to the pipe, and also sets "1" in the OVRN bit. Moreover, when a packet error is detected in the reception data related to the In-token, "1" is also set to the CRCE bit. (b) In a transfer type pipe that is not isochronous, when a case occurs continuously three times in any combination where the Peripheral device does not respond to the In-token issued by the controller (detected a timeout without detecting a handshake packet from the Peripheral device) or an error is detected in the Peripheral device packet. The controller sets "1" to the PIPENRDY bit corresponding to the pipe, and modifies the PID bit of the corresponding pipe to "NAK". (c) In an isochronous transfer type pipe, when the Peripheral device does not respond to the In-token (a timeout is detected without detecting a data packet from the Peripheral device), or when an error occurs in the Peripheral device packet. In this case, the controller sets "1" to the PIPENRDY bit corresponding to the pipe (the PID bit of the corresponding pipe is not modified). (d) In an isochronous transfer type pipe, when a CRC error or bit stuffing error is detected in the received packet. In this case, the controller sets "1" to the PIPENRDY bit corresponding to the pipe and sets "1" to the CRCE bit. (e) When a STALL handshake is received. In this case, the controller sets "1" in the PIPENRDY bit corresponding to the pipe, and modifies the PID bit of the corresponding pipe to "1". Rev1.01 Oct 17, 2008 page 64 of 183 R8A66597FP/DFP/BG 2.11.22.2 When the Host Controller function is selected, and the connection where a split transaction occurs (1) When the pipe is transmitting (a) In an isochronous transfer type pipe, when the time reaches the Out-token issue timing where transmission data does not exist in the FIFO buffer. Here, while issuing the Start-Split (S-Split) transaction, it sets "1" to the PIPENRDY bit corresponding to the pipe, and sets "1" in the OVRN bit. It also sends a zero-length packet in continuation with the Out-token. (b) In a transfer type pipe that is not isochronous, when a case occurs continuously three times in any combination where the Hub does not respond to S-Split or Complete-Split (C-Split) transactions (detected timeout without detecting a handshake packet from the hub) or an error has been detected in the hub packet. Here, the controller sets "1" to the bit corresponding to the PIPENRDY bit and modifies the PID bit of the corresponding pipe to "NAK". When a NRDY interrupt is detected during a C-Split issue, the controller clears the CSSTS bit to "0" and sets it. (c) When a STALL handshake is received for the C-Split. In this case, the controller sets "1" to the PIPENRDY bit corresponding to the pipe, modifies the PID bit of the corresponding file to "STALL(11)", and clears the CSSTS bit to "0" and sets it. (d) In an interrupt transfer type pipe, when a NYET is received for the C-Split and the microFrame number is "4". This controller sets "1" to the PIPENRDY bit corresponding to the pipe, it clears the CSSTS bit to "0" and sets it (the PID bit of the corresponding pipe is not modified). (2) When the pipe is receiving (a) In an isochronous transfer type pipe, the time reaches the In-token issue timing when there is no space in the FIFO buffer. Here, the controller sets "1" to the PIPENRDY bit corresponding to the pipe when a C-Split or S-Split is issued, and sets "1" to the OVRN bit. It also deletes the reception data related to the In-token. (b) In pipe transfer of bulk transfer type or in transfer other than Setup transaction of DCP, when a C-Split or S-Split is issued, and when a case occurs continuously three times in any combination where the Hub does not respond to the In-token issued by the controller (detected timeout without detecting Hub DATA packet), or an error has been detected in the Hub packet. Here the controller sets "1" to the PIPENRDY bit corresponding to the pipe and modifies the PID bit of the corresponding pipe to "NAK". When these conditions occur in a C-Split, the controller clears the CSSTS bit to "0" and sets it. (c) In C-Split of pipe of isochronous transfer type or Interrupt, when a case occurs continuously three times in any combination where the Hub does not respond to the In-token issued by the controller (a detected timeout without detecting the DATA packet from the Hub), or an error has been detected in the Hub packet. In the pipe of Interrupt transfer type, when these conditions occur, the controller sets "1" to the PIPENRDY bit corresponding to the pipe, modifies the PID bit of the corresponding pipe to "NAK", and clears the CSSTS bit to "0". In the pipe of isochronous transfer type, when these conditions occur, the controller sets "1" to the PIPENRDY bit corresponding to the pipe, sets "1" to the CRCE bit, clears the CSSTS bit to "0" and sets it (the PID bit of the pipe is not modified). (d) In a C-Split of pipe of transfer type other than isochronous, when a STALL handshake is received, the controller sets "1" to the PIPENRDY bit corresponding to the pipe, modifies the PID bit of the orresponding pipe to "STALL(11)", clears the CSSTS bit to "0" and sets it. (e) In a C-Split of pipe of transfer type isochronous/Interrupt, when a NYET handshake is received when Microframe is "4". The controller sets "1' in the PIPENRDY bit corresponding to the pipe, sets "1" to the CRCE bit, clears the CSSTS bit to "0" and sets it (the PID bit of the pipe is not modified). Rev1.01 Oct 17, 2008 page 65 of 183 R8A66597FP/DFP/BG 2.11.22.3 Peripheral Controller function selection (1) When the pipe is transmitting: (a) When an IN Token is received while there is no transmission data in the FIFO buffer and the corresponding PIPE PID bit is set to "BUF" ("01"): While receiving the In-token, the controller issues an NRDY interrupt and sets "1" to the PIPENRDY bit. If the interrupt pipe transfer type is isochronous, the controller sends a zero-length packet and sets "1" to the OVRN bit. (2) When the pipe is receiving: (a) When the corresponding PIPE PID bit is set to "BUF" ("01") and an OUT Token is received while there is no open space in the FIFO buffer: If an interrupt pipe transfer type is isochronous, when the Out-token is received, the controller issues a NRDY interrupt, sets "1" to the PIPENRDY bit and sets "1" to the OVRN bit. If the interrupt pipe transfer type is not isochronous, the controller issues a NRDY interrupt request while sending a NAK handshake after receiving the data in continuation with an Out-token, and sets "1" to the PIPENRDY bit. However, while resending (when DATA-PID mismatch occurs), a NRDY interrupt request is not issued. If there is a data packet error, the request is not issued. (b) When the corresponding PIPE PID bit is set to "BUF" ("01") and a PING token is received while there is no open space in the FIFO buffer: While receiving the PING-token, the controller issues NRDY interrupt and sets "1" to the PIPENRDY bit. (c) In an Isochronous transfer PIPE, when the PID bit is set to "BUF" ("01") and data is not received successfully within the interval frame: The controller issues NRDY interrupt request and sets "1" to the PIPENRDY bit in the SOF reception timing. Rev1.01 Oct 17, 2008 page 66 of 183 R8A66597FP/DFP/BG BEMP interrupt status register [BEMPSTS] 15 14 13 12 11 10 ? ? Bit ? ? ? ? ? ? Name ? ? ? ? 9 0 - 8 0 - 7 0 Function 6 0 - 5 4 PIPEBEMP 0 0 - 3 0 - 2 0 - Software Hardware Remarks 15-10 Unassigned. Fix to "0". 9-0 BEMP interrupt status of each pipe is set. PIPENRDY 0:interrupt not issued BEMP interrupt status of each pipe 1:interrupt issued R/W(0) W(1) Remarks * Bit number corresponds to the pipe number. To clear the status shown by each bit of this register, write "0" only for the bit to be cleared and "1" for the other bits. 2.11.23 BEMP interrupt status bit of each pipe (PIPEBEMP) For the pipe set as "PID=BUF" by the software, when the controller uses the software to detect the BEMP interrupt, it sets "1" to the bit corresponding to the BEMPENB register. In this case, when using the software to write "1" to the bit corresponding to the BEMPENB register, the controller sets "1" to the INTSTS0 register BEMP bit and asserts the interrupt from the INT_N pin. The controller issues an internal BEMP interrupt request in the following cases: (1) In the transmission pipe, when the FIFO buffer of the corresponding pipe is empty on completion of transmission (including transmission of the zero-length packet). When it is a single buffer setting, for the pipe other than the DCP, the internal BEMP interrupt request is issued simultaneously with the BRDY interrupt. However, the internal BEMP interrupt request is not issued in the following cases: (a) If writing to a double buffer, when the software (DMAC) starts the data write for the FIFO buffer on the CPU side after completion of data transmission on one side. (b) Buffer clear by writing "1" to the ACLRM bit or BCLR bit (empty). (c) If writing to the Peripheral Controller function, IN transfer of control transfer status stage (zero-length packet transmission) (2) In the receiving pipe When the data size greater than the setup value of the maximum packet size is received normally. In this case, the controller issues the BEMP interrupt request, sets "1" in the bit corresponding to the PIPEBEMP bit, deletes the reception data, and modifies the PID bit to "STALL"("11")". The controller does not give any response if writing to the Host Controller function, and gives a STALL response if writing to the Peripheral Controller function. However, the internal BEMP interrupt request is not issued in the following cases: (a) When a CRC error or bit stuffing error, etc., have been detected in the reception data (b) While executing a Setup transaction The status can be cleared by writing "0" to this bit. No process is executed even if "1" is written to this bit. Rev1.01 Oct 17, 2008 page 67 of 183 R8A66597FP/DFP/BG 2.12 Frame Number Register Frame number register [FRMNUM] 15 14 13 12 11 OVRN CRCE 0 0 ? ? ? ? ? ? Bit Name 10 0 - 9 0 - 8 0 - 7 0 Function 6 0 - 5 FRNM 0 - 4 0 - 3 0 - 2 0 - Software Hardware Remarks R/W(0) W Whether Overrun/Underrun error is detected or not is OVRN set for the pipe transferred isochronously. 15 Overrun/Underrun detect status 0: No error 1: Error Whether CRC error is detected or not is set for the CRCE pipe transferred isochronously. 14 CRC error detect status 0: No error 1: Error 13-11 Unassigned. Fix to "0". 10-0 FRNM Frame number Latest frame number is displayed. R/W(0) W R W Remarks * The OVRN bit is used for debugging. Set the timing so that an Overrun/Underrun error does not occur in the system. 2.12.1 Overrun/Underrun detection status bit (OVRN) In an isochronous transfer type pipe, the controller sets "1" to this bit when an Overrun/Underrun is detected. When an Overrun/Underrun is detected, the controller issues an internal NRDY request. Refer to 2.11.22 for details. The software can clear this bit to "0" by writing "0" to this bit. In this case, write "1" to other bits of this register". 2.12.1.1 Host Controller function selection The controller sets "1" to this bit in either of the following cases: (1) When data has not been written completely to the FIFO buffer despite transmission, and the Out-token issued timing has been attained in the isochronous transfer type transmission pipe. (2) When at least one part of the FIFO buffer is not free, and the In-token issued timing has been attained in the isochronous transfer transmission pipe. 2.12.1.2 Peripheral Controller function selection The controller sets "1" to this bit in either of the following cases: (1) When data has not been written completely to the FIFO buffer despite transmission, and the Out-token is received in the isochronous transfer type transmission pipe. (2) When at least one part of the FIFO buffer is not free, and the Out-token is received in the isochronous transfer receiving pipe. 2.12.2 CRC error detection status bit (CRCE) In an isochronous transfer pipe, the controller sets "1" to the bit when a CRC error or bit stuffing error has been detected. The software can clear this bit to "0" by writing "0" to this bit. In this case, write "1' to other bits of this register". When a CRC error or bit stuffing error is detected, the controller issues an internal NRDY request. Refer to 2.11.22 for details. Rev1.01 Oct 17, 2008 page 68 of 183 R8A66597FP/DFP/BG 2.12.3 Frame number bit (FRNM) The controller updates the SOF issue timing every 1ms or updates this bit during SOF reception, and sets the frame number. Check the consistency twice during read of this bit by the software. Rev1.01 Oct 17, 2008 page 69 of 183 R8A66597FP/DFP/BG frame number register [UFRMNUM] 15 14 13 12 11 ? ? Bit UFRNM Microframe ? ? ? ? Name ? ? ? ? 10 ? ? 9 ? ? 8 ? ? 7 ? ? 6 ? ? 5 ? ? 4 ? ? 3 ? ? 2 0 - Function Software Hardware 15-3 Unassigned. Fix to "0". 2-0 Microframe number is set. R W Remarks None 2.12.4 Microframe number bit (UFRMNUM) When the speed of either Port0 or Port1 is Hi-Speed, the controller displays the Microframe number in this bit. When the speed of both Port0 and Port1 is other than Hi-Speed, the controller sets 0x00 to this bit. Use software to check the consistency twice when this bit is being read. Rev1.01 Oct 17, 2008 page 70 of 183 R8A66597FP/DFP/BG 2.13 USB Address When the Peripheral Controller Function is Selected USBAddress register [USBADDR] 15 14 13 12 11 ? ? Bit ? ? ? ? Name ? ? ? ? 10 ? ? 9 ? ? 8 ? ? 7 ? ? Function 6 0 0 5 0 0 4 3 2 USBADDR 0 0 0 0 0 0 Software Hardware Remarks P (Read value invalid when H) 15-7 Unassigned. Fix to "0". USBADDR USBAddress When Peripheral Controller function is selected, USB address confirmation assigned from the host is set. 6-0 R R/W Remarks 2.13.1 USB address bit (USBADDR) When the Peripheral Controller function is selected, the USB address received in this bit is set when the set address request is processed normally by the controller. When the Peripheral Controller function is selected, if a USB reset is detected by the controller, 0x00 is set to this bit. When the Host Controller function is selected, the controller does not use this bit. Rev1.01 Oct 17, 2008 page 71 of 183 R8A66597FP/DFP/BG 2.14 USB Request Register The USB request register is the register for saving the control transfer Setup request. When the Peripheral Controller function is selected, the received USB request value is stored. When the Host Controller function is selected, set the USB request to be sent. USB request type register [USBREQ] 15 14 13 12 11 bRequest 0 0 0 0 0 0 0 0 0 0 Bit 15-8 7-0 bRequest request bmRequest type request type Name 10 0 0 9 0 0 8 0 0 7 0 0 Function 6 0 0 5 0 0 4 3 bmRequestType 0 0 0 0 Software When P:R When H:R/W When P:R When H:R/W 2 0 0 Hardware When P:W When H:R When P:W When H:R USB request bRequest value USB request bmRequest type value Remarks None 2.14.1 USB request bit (bRequest) 2.14.1.1 Selecting the Host Controller function Use the software to write to the USB request data value of the Setup transaction to be sent. Use the software to write "SUREQ=1", but do not write the bit for the period until "SUREQ=0" is set by the controller. 2.14.1.2 Selecting the Peripheral Controller function The USB request data value received in the Setup transaction by the controller is displayed in this bit. It is not possible (invalid) to write to this bit using the software. 2.14.2 USB request bit (bRmRequestType) 2.14.2.1 Selecting the Host Controller function Use the software to write to the USB request data value of the Setup transaction to be sent. Use the software to write "SUREQ=1", but do not write the bit for the period until "SUREQ=0" is set by the controller. 2.14.2.2 Selecting the Peripheral Controller function The USB request data value received in the Setup transaction by the controller is set to this bit. It is not possible (invalid) to write to this bit using the software. Rev1.01 Oct 17, 2008 page 72 of 183 R8A66597FP/DFP/BG USB request value register [USBVAL] 15 14 13 12 11 0 0 Bit wValue 15-0 Value Remarks None 0 0 0 0 Name 0 0 0 0 10 0 0 9 0 0 Function 8 7 wValue 0 0 0 0 6 0 0 5 0 0 Software 4 0 0 3 0 0 2 0 0 Hardware USB request wValue value When P:R When H:R/W When P:W When H:R 2.14.3 Value bit (wValue) This is the bit to write and read the value of the USB request wValue. b7-0 is a lower byte. 2.14.3.1 Selecting the Host Controller function Use the software to write the value of the USB request wValue of the Setup transaction to be sent. Use the software to write "SUREQ=1", but do not rewrite this bit until "SUREQ=0" is set by the controller. 2.14.3.2 When the Peripheral Controller function is selected The USB request wValue value received in the Setup transaction by the controller is set in this bit. It is not possible (invalid) to write to this bit using the software. USB request index register [USBINDX] 15 14 13 12 11 10 0 0 Bit 15-0 wIndex Index 0 0 0 0 Name 0 0 0 0 0 0 9 0 0 8 7 wIndex 0 0 0 0 Function 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 Software When P:R When H:R/W Hardware When P:W When H:R USB request wIndex value Remarks None 2.14.4 Index bit (wIndex) This is the bit to write and read the value of the USB request wIndex. b7-0 is a lower byte. 2.14.4.1 Selecting the Host Controller function Use the software to write the value of the USB request wIndex of the Setup transaction to be sent. Use the software to write "SUREQ=1", but do not rewrite this bit until "SUREQ=0" is set by the controller. 2.14.4.2 Selecting the Peripheral Controller function The USB request wIndex value received in the Setup transaction by the controller is set in this bit. It is not possible (invalid) to write to this bit using the software. Rev1.01 Oct 17, 2008 page 73 of 183 R8A66597FP/DFP/BG USB request index register [USBLENG] 15 14 13 12 11 10 0 0 Bit 15-0 wLength Length 0 0 0 0 Name 0 0 0 0 0 0 9 0 0 8 7 wLength 0 0 0 0 Function 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 Software When P:R When H:R/W Hardware When P:W When H:R USB request wLength value Remarks None 2.14.5 Length bit (wLength) This is the bit to write and read the value of the USB request wLength. b7-0 is a lower byte. 2.14.5.1 Selecting the Host Controller function Use the software to write the value of the USB request wIndex of the Setup transaction to be sent. Use the software to write "SUREQ=1", but do not rewrite this bit until "SUREQ=0" is set by the controller. 2.14.5.2 Selecting the Peripheral Controller function The USB request wLength value received in Setup transaction by the controller is set in this bit. It is not possible to write to this bit using the software. Rev1.01 Oct 17, 2008 page 74 of 183 R8A66597FP/DFP/BG 2.15 DCP Configuration When using the control transfer for data communication, use the default control pipe (DCP). DCP configuration register [DCPCFG] 15 14 13 12 11 ? ? Bit ? ? ? ? Name ? ? ? ? 10 ? ? 9 ? ? 8 7 6 ? ? 5 ? ? CNTMD SHTNAK 0 0 - 4 DIR 0 - 3 ? ? 2 ? ? Function Software Hardware R/W R 15-5 Unassigned. Fix to "0". Specifies whether to connect the pipe in continuous transfer mode. 8 0: Non-continuous transfer mode 1: Continuous transfer mode For pipe reception direction, specifies whether to modify SHTNAK PID to NAK during transfer end. 7 Pipe disabled at the end of 0: Pipe continued at end of transfer transfer 1: Pipe disabled at end of transfer 3-0 Unassigned. Fix to "0". Set transfer direction of data stage and status stage of DIR control when the Host Controller function is selected. 4 Transfer register 0: Data reception direction 1: Data transmission direction 3-0 Unassigned. Fix to "0". CNTMD Continuous transfer mode Remarks None R/W R R/W R H (Write to "0" when P) 2.15.1 Transfer direction bit (DIR) Set transfer direction of data stage and status stage of control when the Host Controller function is selected. When the Peripheral Controller function is selected, write "0" to this bit. 2.15.2 Continuous transfer mode bit (CNTMD) According to the setup value of this bit, this controller determines transmission/reception completion for the FIFO buffer assigned to the selected pipe, as shown in Table 2.14. Table 2.14 Relation Between Transmission/Reception Completion Determination for the CNTMD Setup Value and the FIFO Buffer CNTMD bit Setup value 0 Read Possible status and method to determine transmission possibility If the transfer direction has been set to reception, the condition when the status of the FIFO buffer changes to Read Possible. When the controller has received one packet. If the transfer direction has been set to transmission, the condition when the status of the FIFO buffer changes to Transmission Possible. When following conditions are fulfilled: (1) The software has written the data of maximum packet size in the FIFO buffer. (2) The software has written the data of short packet (including the case of 0 byte) and "BVAL=1". If the transfer direction has been set to reception, conditions for the FIFO buffer to change to Read Enabled status are: (1) When 256bytes of received data in the specified FIFO buffer (2) When the controller receives a short packet other than a zero-length packet (3) When the contoller receives a Zero-Length packet even though data is already stored in the specified FIFO buffer of the selected PIPE0. If the transfer direction has been set to transmission, the condition when the status of the FIFO buffer changes to Transmission Possible. When (1), or (2) from the following conditions is fulfilled: (1) When the data count written by the software does not match with one side of FIFO buffer size assigned to the selected pipe. (2) When the software writes the data (including 0 bytes) smaller than the data on one side of FIFO buffer Oct 17, 2008 page 75 of 183 1 Rev1.01 R8A66597FP/DFP/BG assigned to the selected pipe0 and "BVAL=1". When the Host Controller function is selected, if the DIR bit is set to "0" the transfer direction is reception and If the DIR bit is set to "1" it is transmission. When the Peripheral Controller function is selected, if the ISEL bit is set to "0" the transfer direction is reception and If the ISEL bit is set to "1" it is transmission. This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written to. Execute USB communication using the selected pipe, use the software to continuously write "ACLRM=1" and "ACLRM=0", clear the FIFO buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. To modify this bit after changing the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary tto check the PBUSY bit. 2.15.3 Pipe disabled at the end of transfer bit (SHTNAK) This bit is valid when DCP is receiving. When the software has set "1" to this bit for the receiving pipe, when the transfer end, the controller modifies the PID bit of the DSP to "NAK". The controller determines transfer end when the following conditions are fulfilled: (1) When a short packet data (including a zero-length packet) is received normally. This bit can be modified when "CSSTS=0" and "PID=NAK". To modify this bit after changing the PID bit of the DCP from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. Write "0" to this bit for the transmission direction pipe". 2.15.4 Transfer direction bit (DIR) Set transfer direction of data stage and status stage of control when the Host Controller function is selected. When the Peripheral Controller function is selected, write "0" to this bit. Rev1.01 Oct 17, 2008 page 76 of 183 R8A66597FP/DFP/BG DCP maximum packet size register [DCPMAXP] 15 14 13 12 11 10 9 DEVSEL 0 0 0 0 ? ? ? ? ? ? Bit Name 8 ? ? Function 7 ? ? 6 1 - 5 0 - 4 0 - 3 MXPS 0 - 2 0 - Software Hardware Remarks 15-12 DEVSEL Device select When the Host Controller function is selected, specify the Peripheral device address of the communication partner of control transfer. 0000: Address"0000" 0001: Address"0001" ... 1001: Address"1001" 1010: Address"1010" 1011-1111: Reserved This specifies the maximum payload (maximum packet size) for the DCP. R/W R H (Write all "0" when P) 11-7 Unassigned. Fix to "0". 6-0 MXPS Maximum packet size R/W R Remarks None 2.15.5 Device select bit (DEVSEL) When the Host Controller function is selected, write to the USB device address of the communication partner in this bit. Write to this bit after writing to the DEVADDx register corresponding to the setup value of this bit. For example, while writing "DEVSEL=0010", write the DEVADD2 address of the H'D4 address. Not write to this bit except when "CSSTS=0", "PID=NAK", and "SUREQ=0". To modify this bit after changing thePID bit of the DCP from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0" and then modify the bit. However, when the controller modifies the PID bit to "NAK", it is not necessary to check the PBUSY bit. When the Peripheral Controller function is selected, write "0000" to this bit. 2.15.6 Maximum packet size bit (MXPS) Write the maximum data payload of the DCP (maximum packet size) to this bit. 0x40 (64 bytes) is the default value. Set the values according to the USB Specification Revision 2.0 while writing the MXPS bit. Not write to the MXPS bit except when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written. To modify this bit after changing the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify the bit. However, when the controller modifies the PID bit to "NAK", it is not necessary to check the PBUSY bit. When "MXPS=0" is written, do not write to the FIFO buffer or write "PID=BUF". Rev1.01 Oct 17, 2008 page 77 of 183 R8A66597FP/DFP/BG DCP control register [DCPCTR] 15 14 13 12 11 BSTS SUREQ CSCLR CSSTS SUREQCLR 0 0 0 0 0 - 10 ? ? 9 ? ? 8 7 6 5 4 3 ? ? 2 CCPL 0 0 PID 0 0 0 0 SQCLR SQSET SQMON PBUSY PINGE 0 0 1 0 0 - Bit 15 BSTS Buffer status Name Function Software Hardware Remarks R W H (Write to "0" when P) H (Write to "0" when P") H (Invalid read value when P) H (Write to "0" when P") Access possibility status of DCP FIFO buffer is set. 0: Buffer access is disabled 1: Buffer access is enabled When the Host Controller function is selected, the Setup SUREQ packet is transmitted by writing "1" to this bit. 14 Setup token transmit 0: Invalid 1: Transmit Setup packet When the Host Controller function is selected, regarding the transfer using Split Transaction, the CSSTS bit can CSCLR be cleared to "0" by writing "1" to this bit. In this case, the 13 CSPLIT status clear of split next DCP transfer restarts from SSPLIT. transaction 0: Invalid 1: Clear CSSTS bit When the Host Controller is selected, the split transaction C-SPLIT status is set. CSSTS 0: During the Start-Split (S-SPLIT) transaction process or 12 Complete split (C-SPLIT) status during the process of the device in which the split of split transaction transaction is not used 1: During the C-SPLIT transaction process When the Host Controller is selected, the SUREQ bit can SUREQCLR be cleared by writing "1" to this bit. 11 SUREQ bit clear 0: Invalid 1: Clear SUREQ bit to "0" 10-9 Unassigned. Fix to "0". In DCP transfer, the expected value of sequence toggle SQCLR bit of next transaction can be written to DATA0. 8 Toggle bit clear 0: Invalid 1: Specifies DATA0 In the DCP transfer, the expected value of the sequence toggle bit of the next transaction can be written to SQSET 7 DATA1. Toggle bit set 0: Invalid 1: Specifies DATA1 In the DCP transfer, the expected value of the sequence SQMON toggle bit of the next transaction is set. 6 Sequence toggle bit monitor 0: DATA0 1: DATA1 When the PID bit of the DCP is modified from BUF to NAK, it is written to whether the actual communication of SPBUSY 5 the DCP is transited to NAK status or not. Pipe busy 0: Transition to NAK is incomplete 1: Transition to NAK is complete When the Host Controller function is selected, the PING token can be used in an OUT transaction by writing "1" PINGE 4 to this bit. PING token issue enabled 0: PING token issue disabled 1: Normal PING operation 3 Unassigned. Fix to "0". When the Peripheral Controller function is selected, status stage end of control transfer is enabled by writing CCPL 2 "1" to this bit. Control transfer end enabled 0: Invalid 1: Control transfer end enabled R/W(1) R/W(0) R(0)/W(1) R/W(0) R R/W R(0)/W(1) R/W(0) R(0)/W(1) R R(0)/W(1) R R W R W R/W R H (Write to "0" when P") R(0)/W(1) R/W(0) P (Write to "0" when P") Rev1.01 Oct 17, 2008 page 78 of 183 R8A66597FP/DFP/BG Bit Name Function This bit controls the controller response in the control transfer. 00: NAK response 01: BUF response (conforms with the buffer state) 10: STALL response 11: STALL response Software Hardware Remarks 1-0 PID Response PID R/W R/W Remarks None 2.15.7 Buffer status bit (BSTS) The controller indicates by this bit whether access of the FIFO buffer assigned to the DCP is possible from the CPU. The meaning of this bit differs according to the setup value of the ISEL bit as follows: (1) When "ISEL=0": Indicates whether read of reception data is possible. (2) When "ISEL=1": Indicates whether write of transmission data is possible. 2.15.8 Setup token transmission bit (SUREQ) When the Host Controller function is selected, the controller transmits a Setup packet by using the software to write "1" to this bit. After the Setup transaction process is completed, the controller issues a SACK interrupt or a SIGN interrupt and writes "0" to this bit. The controller writes "0" to this bit using the software to write "1" to the SUREQCLR bit. Set the USB request to be transmitted to the DEVSEL bit, USBREQ register, USBVAL register, USBINDX register and USBLENG register, and then write "1" to this bit. Check whether the PID bit of the DCP is set to "NAK", and then write "SUREQ=1". Thereafter, do not modify the values of the DEVSEL bit, USBREQ register, USBVAL register, USBINDX register and USBLENG register until the Setup transaction is completed ("SUREQ=1"). Write "1" to this bit only while transmitting the Setup token. In other cases, always write it to "0". When the Peripheral Controller function is selected, write "0" to this bit. Rev1.01 Oct 17, 2008 page 79 of 183 R8A66597FP/DFP/BG 2.15.9 C-SPLIT status clear bit of split transaction (CSCLR) When the Host Controller function is selected, if the software writes "1" to this bit, the controller clears the CSSTS bit to "0". In transfer using Split Transaction, to restart the next transfer forcefully from S-Split, write "1" to this bit. In normal Split Transactions, since the controller clears the CSSTS bit automatically to "0" when the C-Split ends, the clear process by the software is not required. Control the CSSTS bit by using it when the communication is stopped by "UACT=0" or when it is confirmed that transfer is not complete due to detach detection. When "CSSTS=0", it remains "CSSTS=0" even if "1" is written to this bit. When the Peripheral Controller function is selected, write "0" to this bit. 2.15.10 C-SPLIT status bit of split transaction (CSSTS) When the Host Controller function is selected, the controller sets the C-Split status of the split transaction to this bit. The controller sets "1" to this bit while starting the C-Split, and sets "0" when the C-Split end is detected. Setting this bit sets a valid value only when the Host Controller function is selected. 2.15.11 SUREQ clear bit (SUREQCLR) When the Host Controller function is selected, if the software writes "1" to this bit, the controller clears the SUREQ bit to "0". The controller always sets this bit to "0". In the Setup transaction, when communication is stopped by writing "SUREQ=1" without modifications, use the software to write "1" to this bit. In the usual Setup transaction, since the controller clears the SUREQ bit automatically to "0" when the transaction ends, the clear process by the software is not required. Control the SUREQ bit by using this bit when the communication is stopped by "UACT=0", or when it is confirmed that transfer is not complete due to detach detection. When the Peripheral Controller function is selected, write "0" to this bit. 2.15.12 Clear bit of sequence toggle bit (SQCLR) If the software writes "1" to this bit, the controller writes the expected value of the sequence toggle bit of the pipe to DATA0. The controller always sets "0" to this bit. Do not write "1" to the SQCLR bit and SQSET bit simultaneously. Write "1" to this bit when "CSCTS=0", "PID=NAK" and "when not set to CURPIPE". To write "1" to this bit after modifying the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then write the bit. However, since the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. Rev1.01 Oct 17, 2008 page 80 of 183 R8A66597FP/DFP/BG 2.15.13 Sequence toggle bit set bit (SQSET) If the software writes "1" to this bit, the controller writes the expected value sequence toggle bit of the pipe to DATA1. The controller always sets "0" to this bit. Do not write "1" to the SQCLR bit and SQSET bit simultaneously. Write "1" to this bit when "CSCTS=0", "PID=NAK" and "when not set to CURPIPE". To write "1" to this bit after the PID bit of the corresponding pipe is modified from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0" and then modify the bit. However, if the controller modifies the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.15.14 Sequence toggle bit monitor bit (SQMON) The controller sets the expected value of the sequence toggle bit of the pipe in this bit. If a normal process is executed for the transaction, the controller toggles this bit. However, the bit is not toggled when a DATA-PID mismatch occurs during reception transfer. When the Peripheral Controller function is selected, the controller writes "1" to this bit (writes the expected value to "1") when the Setup packet is received normally. When the Peripheral Controller function is selected, the controller does not refer to this bit during IN/OUT transaction of the status stage. It does not toggle the bit even if the process is completed normally. 2.15.15 Pipe busy bit (PBUSY) The controller modifies this bit from "0" to "1" when the USB transaction of the pipe is started. This bit is modified from "1" to "0' when one transaction is complete. When the software has written "PID=NAK", it is possible to check whether the pipe setting can be modified by reading this bit. 2.15.16 PING token issue enabled bit (PINGE) When the Host Controller function is selected, if the software writes "1" to this bit, the controller issues a PING token during the transmission transfer. The transmission transfer starts from the PING transaction. When an ACK handshake is detected in the PING transaction, an OUT transaction is executed in the next transaction. When a NAK handshake is detected in the OUT transaction, a PING transaction is executed in the next transaction. When the Host Controller function is selected, if the software writes "0" to this bit, the controller does not execute the PING token in the transmission transfer. The entire transmission transfer is executed in the OUT transaction. This bit can be modified when "CSSTS=0" and "PID=NAK". To write "1" to this bit after modifying the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then write the bit. However, when the controller modifies the PID bit to "NAK", is it not necessary to check the PBUSY bit. Rev1.01 Oct 17, 2008 page 81 of 183 R8A66597FP/DFP/BG 2.15.17 Control transfer end enabled (CCPL) When the Peripheral Controller function is selected, if the corresponding PID bit is "BUF" and the software writes "1" to this bit, the controller completes the control transfer stage. In other words, it transmits an ACK handshake for the OUT transaction from the USB Host during a Control Read Transfer, and transmits a zero-length packet for an IN transaction from the USB Host during a Control Write and No Data Control Transfer. However, irrespective of the setup value of this bit, the controller responds automatically from the Setup stage until the status stage is complete when a SET_ADDRESS request is detected. When a new Setup packet is received, the controller modifies this bit from "1" to "0". When "VALID=1", the software cannot write "1" to this bit. When the Host Controller function is selected, write "0" to this bit. 2.15.18 Response PID bit (PID) For this bit, while executing data stage or status stage of control transfer, use the software to modify this bit from "NAK" to "BUF". 2.15.18.1 When the Host Controller function is selected Use the procedure below to modify this bit from "NAK" to "BUF": (1) When setting transmission direction When "UACT=1" and "PID=NAK", complete the write of transmission data in the FIFO buffer and then write "PID=BUF". Thereafter, the controller executes an OUT transaction (or PING transaction). (2) When setting reception direction When "UACT=1" and "PID=NAK", check to see that the FIFO buffer is empty (change the status to empty) and write "PID=BUF". Thereafter, the controller executes an IN transaction. The controller changes the value of this bit in any of the following cases: (1) When the software has written "BUF" to this bit and the controller receives the data exceeding the maximum packet size, the controller sets "PID=STALL(11)". (2) When a reception error such as a CRC error has been detected three times continuously, the controller sets "PID=NAK". (3) When a STALL handshake is received, the controller sets "PID=STALL(11)". After an S-Split execution of a Split transaction in the pipe (when the controller sets CSSTS="1"), the controller executes the transaction until the C-Split ends, even if the software has modified this bit to "NAK". The controller sets "PID=NAK" when the C-Split ends. 2.15.18.2 When the Peripheral Controller function is selected The controller modifies the bit value in the following cases: (1) When the controller receives the Setup packet, the controller modifies this bit to "NAK" ("00"). Here, the controller sets "VALID=1" and the software cannot modify this bit until it writes "VALID=0". (2) When the software writes "BUF" to this bit and the controller receives the data exceeding the maximum packet size, the controller sets "PID=STALL(11)". (3) When the controller detects a control transfer sequence error, it sets "PID=STALL(1x)". (4) When the controller detects a USB bus reset, it sets "PID=NAK". During a SET_ADDRESS request process (auto process), the controller does not refer to the setup value of this bit. Rev1.01 Oct 17, 2008 page 82 of 183 R8A66597FP/DFP/BG 2.16 Pipe Configuration Register Pipe1 - Pipe9 should be written to using the PIPESEL, PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPExCTR, PIPExTRE and PIPExTRN registers. After selecting the pipe using the PIPESEL register, write to the pipe functions using the PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI registers. The PIPExCTR, PIPExTRE and PIPExTRN registers can be written to separately from the pipe selection specified with the PIPESEL register, with no relation between them. Pipe window selection register [PIPESEL] 15 14 13 12 11 10 ? ? Bit ? ? ? ? Name ? ? ? ? ? ? 9 ? ? 8 ? ? 7 ? ? Function 6 ? ? 5 ? ? 4 ? ? 3 0 - Software Hardware Remarks 15-4 Unassigned. Fix to "0". Specifies pipe related to Address68H-6EH register. 0000: Not selected 0001: Pipe1 0010: Pipe2 0011: Pipe3 0100: Pipe4 0101: Pipe5 0110: Pipe6 0111: Pipe7 1000: Pipe8 1001: Pipe9 3-0 PIPESEL Pipe window selection R/W R Remarks * When "PIPESEL=0000", "0" is read from all of the bits of the related registers noted above. When "PIPESEL=0000", write to the pipe related to Address68H-6EH register is invalid. 2.16.1 Pipe window selection bit (PIPESEL) If the software writes "0001" to "1001" to this bit, the controller displays the pipe information and the setup value corresponding to the registers from address H68 to H6C. After pipe specification writing of this bit, the value written by the software in address H68 to H6C is reflected in the corresponding pipe transfer method. If the software writes "0000" to this bit, the controller setss all "0" in the register from address H68 to H6C. Using software to write to address H68 to H6C is invalid. Rev1.01 Oct 17, 2008 page 83 of 183 R8A66597FP/DFP/BG Pipe configuration register [PIPECFG] 15 14 13 12 11 10 9 8 7 TYPE BFRE DBLB CNTMD SHTNAK 0 0 ? ? ? 0 0 0 0 ? ? ? Bit Name Function 6 ? ? 5 ? ? 4 DIR 0 - 3 0 - Software Hardware Remarks 15-14 TYPE Transfer type Specifies transfer type of pipe specified in PIPESEL bit. 00: Pipe use disabled 01: Bulk transfer 10: Interrupt transfer 11: Isochronous transfer R/W R 13-11 Unassigned. Fix to "0". Specifies the notification timing related to the pipe from the controller. BFRE 10 0: BRDY interrupt notification upon sending or BRDY interrupt operation specified receiving data 1: BRDY interrupt notification upon reading data Specifies whether the FIFO buffer used by the pipe DBLB is single buffer or double buffer. 9 Double buffer mode 0: Single buffer 1: Double buffer Specifies whether to connect the pipe in continuous CNTMD transfer mode. 8 Continuous transfer mode 0: Non-continuous transfer mode 1: Continuous transfer mode For pipe reception direction, specifies whether to SHTNAK modify PID to NAK during transfer end. 7 Pipe disabled at the end of transfer 0: Pipe continued at end of transfer 1: Pipe disabled at end of transfer 6-5 Unassigned. Fix to "0". Specifies pipe transfer direction. DIR 4 0: Receive Transfer direction 1: Transmit 3-0 EPNUM Endpoint number Specifies endpoint number of pipe. R/W R R/W R R/W R R/W R R/W R/W R R Remarks None Rev1.01 Oct 17, 2008 page 84 of 183 R8A66597FP/DFP/BG 2.16.2 Transfer type bit (TYPE) For this bit, write to USB transfer type of pipe (selected pipe) written to the PIPESEL bit. A list of transfer types that can be written to the selected pipe and this bit are shown in Table 2.15. Table 2.15 List of Transfer Types That Can Be Written To The Selected Pipe & TYPE bit Selected Pipe Pipe1 or Pipe2 Pipe3 ~ Pipe5 Pipe6 ~ Pipe9 TYPE Bit "01" or "11" "01" "10" USB Transfer Type Bulk or isochronous transfer Bulk transfer Interrupt transfer Write a value other than "00" to this bit and then write "PID=BUF" (USB communication is started by writing "PID=BUF" when using the selected pipe). This bit can be modified when the PID bit of the selected pipe is in "NAK" status. To modify this bit after chenging the PID bit of the selected pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify the bit. However, when the controller modifies the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.16.3 BRDY interrupt operation specification bit (BFRE) This bit is valid when the selected pipes are Pipe1 to Pipe5. When the software has written "1" to this bit and the selected pipe is used in reception, (i.e. when "DIR bit=0" is written), the controller detects transfer completion and issues a BRDY interrupt when that packet is completely read. When the BRDY interrupt is issued with these settings, the software need not write "BCLR=1". The status of the FIFO buffer assigned to the selected pipe does not change to receive status until "BCLR=1". The software writes "1" to this bit and the selected pipe is used in transmission, (in other words when "DIR bit=1" is written) the controller does not issue the BRDY interrupt. Refer to the PIPEBRDY interrupt register for details. This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe is in the CURPIPE bit is not written. Execute USB communication by using the selected pipe, use the software to continuously write "ACLRM=1" and "ACLRM=0", clear the FIFO buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. To modify this bit after chenging the PID bit of the selected pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. Rev1.01 Oct 17, 2008 page 85 of 183 R8A66597FP/DFP/BG 2.16.4 Double buffer mode bit (DBLB) This bit is valid when the selected pipe is Pipe1 to Pipe5. When the software writes "1" to this bit, for the selected pipe the controller assigns the FIFO buffer size equal to two sides specified by the PIPEBUF register BUFSIZE bit. In other words, the size of the FIFO buffer that is assigned by the controller to the selected pipe is given below. (BUFSIZE+1)*64*(DBLB+1) [Byte] When the software writes "1" to this bit, and the selected pipe is used in transmission (written to "DIR bit=1"), the controller does not issue a BRDY interrupt. Refer to the PIPEBRDY interrupt register for details. This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written. Execute USB communication using the selected pipe, use the software to continuously write "ACLRM=1" and "ACLRM=0", clear the FIFO buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. Check that "CSSTS=0" and "PBUSY=0", modify the PID bit of the selected pipe from "BUF" to "NAK" and then modify this bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to use the software to check the PBUSY bit. 2.16.5 Continuous transfer mode bit (CNTMD) This bit is valid when Pipe1 to Pipe5 are selected and the transfer type of the selected pipe is set to bulk. According to the setup value of this bit, this controller determines transmission/reception completion for the FIFO buffer assigned to the selected pipe, as shown in Table 2.16. Table 2.16 Relation Between Transmission/Reception Completion Determination for the CNTMD Setup Value and the FIFO Buffer CNTMD bit Setup value 0 Read Possible status and method to determine transmission possibility If the reception has been written ("DIR=0"), the condition when the status of the FIFO buffer changes to Read Possible. When the controller has received one packet. If transmission direction has been written ("DIR=1"), the condition when the status of the FIFO buffer changes to Transmission Possible. When following conditions are fulfilled: (1) The software (or DMAC) has written the data of maximum packet size in the FIFO buffer. (2) The software (or DMAC) has written the data of short packet (including the case of 0 byte) and "BVAL=1". If the reception direction has been written ("DIR=0"), conditions for the FIFO buffer to change to Read Enabled status are: (1) When the number of bytes of received data in the specified FIFO buffer of the selected PIPE matches the set number of bytes ((BUFSIZE+1)*64) (2) When the controller receives a short packet other than a zero-length packet (3) When the contoller receives a Zero-Length packet even though data is already stored in the specified FIFO buffer of the selected PIPE. (4) When the controller receives packets as many as the transaction counter set for the selected pipe. If the transmission direction has been written ("DIR=1"), the condition when the status of the FIFO buffer changes to Transmission Possible. When (1), (2) or (3) from the following conditions is fulfilled: (1) When the data count written by the software (or DMAC) does not match with one side of FIFO buffer size assigned to the selected pipe. (2) When the software (or DMAC) writes the data (including 0 bytes) smaller than the data on one side of FIFO buffer assigned to the selected pipe and "BVAL=1". (3) When the software writes the data (including 0 bytes) smaller than the data on one side of FIFO buffer assigned to the selected pipe and asserts the DENDx_N signal simultaneously with write of the data for the last time. 1 This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written to. Rev1.01 Oct 17, 2008 page 86 of 183 R8A66597FP/DFP/BG Execute USB communication using the selected pipe, use the software to continuously write "ACLRM=1" and "ACLRM=0", clear the FIFO buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. To modify this bit after changing the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary tto check the PBUSY bit. Rev1.01 Oct 17, 2008 page 87 of 183 R8A66597FP/DFP/BG 2.16.6 Pipe disabled at the end of transfer bit (SHTNAK) This bit is valid when Pipe1 to Pipe5 are selected and is receiving. When the software has set "1" to this bit for the receiving pipe, when the transfer end is determined for the selected pipe, the controller modifies the PID bit of the selected pipe to "NAK". The controller determines transfer end when either one of the following conditions are fulfilled: (1) When a short packet data (including a zero-length packet) is received normally. (2) When a transaction counter is used and a packet of transaction counter portion is received normally. This bit can be modified when "CSSTS=0" and "PID=NAK". To modify this bit after changing the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. Write "0" to this bit for the transmission direction pipe". 2.16.7 Transfer direction bit (DIR) When the software has written "0" to this bit and the controller has set the selected pipe to receive and "1" is written to this bit, the controller uses the selected pipe in transmission. This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written. Execute USB communication using the selected pipe, use the software to continuously write "ACLRM=1" and "ACLRM=0", clear the FIFO buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. To modify this bit after changing the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.16.8 Endpoint number bit (EPNUM) In this bit, use the software to write the endpoint number related to the selected pipe. However, writing "0000" indicates that the pipe is not being used. This bit can be modified when "CSSTS=0", "PID=NAK", and when the in the CURPIPE bit is not written. To modify this bit after changing the PID bit of the corresponding pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. Set the combination of the DIR bit and EPNUM bit so that they are not duplicated with the other pipe settings ("EPNUM=000" (selected pipe not used) settings can be duplicated). Rev1.01 Oct 17, 2008 page 88 of 183 R8A66597FP/DFP/BG Pipe buffer specification register [PIPEBUF] 15 14 13 12 11 10 BUFSIZE ? 0 0 0 0 0 ? Bit 15 Name Unassigned. Fix to "0". BUFSIZE Buffer size 9 ? ? 8 ? ? 7 0 - 6 0 - 5 0 - 4 0 - 3 BUFNMB 0 - 2 0 - Function Specifies the FIFO buffer size of pipe specified in PIPESEL bit. 0x00: 64 bytes 0x01: 128 bytes ... 0x1F: 2Kbytes) Specifies the pipe FIFO buffer number. (0x4 - 0x87) Software Hardware Remarks 14-10 R/W R 9-8 Unassigned. Fix to "0". 7-0 BUFNMB Buffer number R/W R Remarks * Not modify each bit in the register except when the status of the software is "CSSTS=0", "PID=NAK" and the pipe is not set in the CURPIPE bit. * To modify each bit in the register after changing the PID bit of the selected pipe from "BUF" to "NAK" check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.16.9 Buffer size bit (BUFSIZE) In this bit, write to the FIFO buffer size to be assigned to the pipe. It is measured in blocks, and one block is 64 bytes. When the software has written "DBLB=1", the controller assigns two sides of the FIFO buffer specified by this bit for the selected pipe. The size of the FIFO buffer that is assigned by the controller to the selected pipe is given below: (BUFSIZE+1)*64*(DBLB+1) [Byte] For this bit, set the values in the following range: (1) When Pipe1 to Pipe5 are selected, the value from 0x0 to 0x1F can be written. (2) When Pipe6 to Pipe9 are selected, only 0x0 can be written. If writing "CNTMD=1", write the value of the integral multiple of the maximum packet size in the BUFSIZE bit. 2.16.10 Buffer number bit (BUFNMB) Specify the first block number from the FIFO buffer to be assigned to the pipe. The block of the FIFO buffer assigned for the selected pipe by the controller is given below: Block number: BUFNMB~block number: BUFNMB+(BUFSIZE+1)*(DBLB+1)-1 For this bit, write the values within the range from 0 (0x00) to 8640 (0x87). However, observe the following conditions: 0x00-0x03 are exclusive to DCP. 0x04 is the dedicated Pipe6. However, when Pipe6 is not used, it can be used by other pipes. When the selected pipe is Pipe6, write to this bit is disabled. The controller automatically assigns "BUFNMB=0x04" to Pipe6. 0x05 is the dedicated Pipe7. However, when Pipe7 is not used, it can be used by other pipes. When the selected pipe is Pipe7, write to this bit is disabled. The controller automatically assigns "BUFNMB=0x05" to Pipe7. 0x06 is the dedicated Pipe8. However, when Pipe8 is not used, it can be used by other pipes. When the selected pipe is Pipe8, write to this bit is disabled. The controller automatically assigns "BUFNMB=0x06" to Pipe8. 0x07 is the dedicated Pipe9. However, when Pipe9 is not used, it can be used by other pipes. When the selected pipe is Pipe9, write to this bit is disabled. The controller automatically assigns "BUFNMB=0x07" to Pipe9. Rev1.01 Oct 17, 2008 page 89 of 183 R8A66597FP/DFP/BG Pipe maximum packet size register [PIPEMAXP] 15 14 13 12 11 10 9 DEVSEL 0 0 0 0 ? 0 0 ? Bit Name 8 0 Function 7 0 - 6 0(1) - 5 MXPS 0 - 4 0 - 3 0 - 2 0 - Software Hardware 15-12 DEVSEL Device select Specifies the device address of the Peripheral when the Host Controller function is selected. 0000:Address"0000" 0001:Address"0001" ... 1001:Address"1001" 1010:Address"1010" 1011 - 1111: Reserved Specifies maximum data payload (maximum packet size) of the pipe. Pipe6 - Pipe9 can be written from 0x1 to 0x40 bytes. R/W R H (Write all "0" when P) 11 10-0 Unassigned. Fix to "0". MXPS Maximum packet size R/W R Remarks * The default value of the MXPS bit is "0x00" when the PIPESEL register PIPESEL pipe is not selected, and "0x40" when selected. 2.16.11 Device select bit (DEVSEL) When the Host Controller function is selected, set the USB device address of the communication partner in this bit. Before write to this bit, the DEVADDx register corresponding to the setup value of this bit is written to. For example, write to the DEVADD2 address of the H'D4 address in order to write "DEVSEL=0010". Not write to this bit except when "CSSTS=0" and "PID=NAK". To modify this bit after changing the PID bit of the pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. When the Peripheral Controller function is selected, write "0000" to this bit. 2.16.12 Maximum packet size bit (MXPS) In this bit, write the maximum data payload (maximum packet size) of the selected pipe. For Pipe1 and Pipe2, the value from 1 byte (0x1) to 1024 bytes (0x400) can be written. For Pipe3 to Pipe5, values of 8 bytes (0x8), 16 bytes (0x10), 32 bytes (0x20), 64 bytes (0x40) and 512 bytes (0x200) can be written (the [2:0] bit does not exist). For Pipe6 to Pipe9, values from 1 byte (0x1) to 64 bytes (0x40) can be written. The default value is 0x40 (64 bytes). In the MXPS bit, write the values based on the USB Specification Revision 2.0 for each transfer type. While transmitting isochronous pipe in Split-Transaction, write the value to less than 188 bytes in the MXPS bit. Not write the MXPS bit except when "CSSTS=0", "PID=NAK" and values are not set in the CURPIPE bit. To modify this bit after chenging the PID bit of the pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. When "MXPS=0", do not write anything in the FIFO buffer and do not write "PID=BUF". Rev1.01 Oct 17, 2008 page 90 of 183 R8A66597FP/DFP/BG Pipe timing control register [PIPEPERI] 15 14 13 12 11 10 IFIS ? ? ? 0 ? ? ? ? ? ? ? Bit Name 9 ? ? 8 ? ? 7 ? ? Function 6 ? ? 5 ? ? 4 ? ? 3 ? ? 2 0 - Software Hardware Remarks P (Write to "0" when H) 15-13 Unassigned. Fix to "0". 12 IFIS Isochronous IN buffer flush Specifies buffer flushed/not-flushed when the transfer type of pipe specified in PIPESEL bit is isochronous IN. 0: The buffer is not flushed 1: The buffer is flushed R/W R 11-3 Unassigned. Fix to "0". 2-0 IITV Specifies the transfer interval timing of pipe as second Interval error detection spacing power frame timing. R/W R Remarks None 2.16.13 Isochronous IN buffer flush bit (IFIS) This is the function in which the controller automatically clears the FIFO buffer when the Peripheral Controller function is selected, if transfer type isochronous pipe, transfer is IN transfer, and when the controller has not received the In-token from the USB Host in the (micro) frame for each interval specified in IITV bit. In the double buffer setting (write "DBLB=1"), the controller clears only the data on one side of the previous buffer. The FIFO buffer is cleared when the SOF packet is received immediately after the (micro) frame receives the In-token. It is cleared also when the SOF packet is corruped when the SOF is to be received by an internal interpolation function. When the Host Controller function is selected, write "0" to this bit. If the selected pipe of other than transfer type isochronous, write "0" to this bit. 2.16.14 Interval error detection spacing bit (IITV) In this bit, specify the interval error detection spacing to frame timing squared. The functional details differ when the Host Controller function and Peripheral Controller function are selected (to be mentioned later). Not write to this bit except when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written. To modify this bit after chenging the PID bit of the pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. When modifying the bit value, after execute USB communication, write "ACLRM=1" after writing "PID=NAK", and initialize the interval timer. This bit does not exist in Pipe3 to Pipe5. Set "0" in the position of the bit corresponding to Pipe3 to Pipe5. Rev1.01 Oct 17, 2008 page 91 of 183 R8A66597FP/DFP/BG 2.16.14.1 When the Host Controller function is selected In case of isochronous or Interrupt transfer type of the selected pipe, values can be written to this bit. The controller controls the token issue interval by the setup value of this bit. The controller issues a token for the selected pipe in one interval with a (micro) frame for 2^IITV times. The controller counts the interval in 1ms frames for the pipe used during the communication between Full-/Low-Speed Peripheral Devices connected to a Hi-Speed HUB. The controller starts counting the token issue spacing from the next (micro) frame after the software writes the PID bit to "BUF". USB bus S O F S O F SO OU FT D A T A 0 SO OU FT D A T A 0 PID bit setup value Token issue flag (0: Issued -: Not issued) Interval counting start NAK - BUF - BUF 0 BUF 0 Figure 2.1 Token issue flag when "IITV=0" USB us S O F S O F SO OU FT D A T A 0 S O F SO OU FT D A T A 0 S O F SO OU FT D A T A 0 PID bit setup value Token issue flag (0: Issued -: Not issued) Interval counting start NAK - BUF - BUF 0 BUF - BUF 0 BUF - BUF 0 Figure 2.2 Token issue flag when "IITV=1" If the transfer type of the selected pipe is an isochronous or interrupt, the controller executes the following operations along with the control of the token issue interval. If the transfer type is isochronous, the controller also issues the token when the NRDY interrupt issue conditions are fulfilled. (1) If the selected pipe is isochronous-IN transfer pipe When an In-token is issued and the packet is not received normally from the Peripheral device (if there is no response or packet error), an NRDY interrupt is issued. Since the FIFO buffer is full (due to reasons like the reading of data from FIFO buffer by the software (DMAC) is slow), the controller sets "1" to the OVRN bit and issues the NRDY interrupt when it cannot receive the data and reaches the In-token issue timing. (2) If the selected pipe is an isochronous-Out transfer pipe When the FIFO buffer contains no data that can be sent (due to reasons like the writing of data in FIFO buffer by the software (DMAC) is slow) and it reaches the Out-token issue timing, the controller displays "1" in the OVRN bit, issues the NRDY interrupt and a zero-length packet is sent. Rev1.01 Oct 17, 2008 page 92 of 183 R8A66597FP/DFP/BG The following are the conditions for resetting the token issuing interval: (1) When the controller is hardware reset (the setup value of IITV is also cleared to"0".) (2) When the software writes "ACLRM=1". Rev1.01 Oct 17, 2008 page 93 of 183 R8A66597FP/DFP/BG 2.16.14.2 When the Peripheral Controller function is selected If the selected pipe transfer type is isochronous, this bit can be written to. (1) If the selected pipe is an isochronous-OUT transfer pipe When the data packet is received in the (micro) frame for each interval set in IITV bit, the controller issues a NRDY interrupt. A NRDY interrupt is also issued when the data packet is not received due to errors such as a CRC error or (due to reasons like the reading of data from FIFO buffer by the software (DMAC) is slow) when the controller cannot receive the data because the FIFO buffer is full. A NRDY interrupt is issued when the SOF packet is received. Also, when the SOF packet is corrupted, the interrupt is issued when the SOF packet is to be received by an internal interpolation function. However, if other than "IITV=0", a NRDY interrupt is to be issued when the SOF packet is received for each interval after starting interval counting. After activating the interval timer, when the PID bit is written to "NAK" by the software, the controller does not issue the NRDY interrupt even if the SOF packet is received. The count start conditions of the interval differ according to the setup value of the IITV bit (a) If "IITV=0": Counting of the interval is started from the next (micro) frame after modifying the PID bit of the selected pipe to "BUF". (Micro) Frame S O F S O F SO OU FT D A T A 0 SO OU FT D A T A 0 PID bit setup value Token reception expectation flag (0: Reception expected -: Not received is expected) Interval counting start NAK - BUF - BUF 0 BUF 0 Figure 2.3 Correlation between (micro) frame and token reception expectation flag when "IITV=0" (b) If other than "IITV=0": Counting of interval is started when the initial DATA packet is received normally after modifying the PID bit of the selected pipe to "BUF". (Micro) Frame S O F S O F SO OU FT D A T A 0 S O F SO OU FT D A T A 0 S O F SO OU FT D A T A 0 PID bit setup value Token reception expectation flag (0: Reception expected -: Not received is expected) Interval counting start NAK - BUF - BUF 0 BUF - BUF 0 BUF - BUF 0 Figure 2.4 Correlation between (micro) frame and token reception expectation flag when "IITV=0" Rev1.01 Oct 17, 2008 page 94 of 183 R8A66597FP/DFP/BG (2) When the selected pipe is an isochronous IN transfer pipe It is used in combination with "IFIS="1". If "IFIS=0", a data packet is sent as a response to the received token, irrespective of the setup value of the IITV bit. If "IFIS=1" is written, the controller clears the FIFO buffer when the FIFO buffer does not contain the data that can be sent, and the In-token is not received in the (micro) frames of each interval set in the IITV bit. It also clears the buffer when the In-token is not received normally due to bus errors, such as a CRC error. The FIFO buffer is cleared when the SOF packet is received. Also, when the SOF packet is corrupted, the FIFO buffer is cleared when the SOF packet is to be received by internal interpolation function. Conditions to start the interval counting differ according to the setup value of IITV bit (similar for OUT). The following are the conditions for counting the interval when the Peripheral Controller function is selected: (a) When this controller is hardware reset (at this point, the setup value of the IITV bit is also cleared to"0"). (b) When the software writes "ACLRM=1". (c) When the controller detects a USB reset. Rev1.01 Oct 17, 2008 page 95 of 183 R8A66597FP/DFP/BG 2.17 Pipe Control Register Pipe1 control register [PIPE1CTR] Pipe2 control register [PIPE2CTR] Pipe3 control register [PIPE3CTR] Pipe4 control register [PIPE4CTR] Pipe5 control register [PIPE5CTR] 15 14 13 12 11 BSTS INBUFM CSSLR CSSTS 0 0 0 0 ? ? 10 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 ? ? 3 ? ? PID ? ? 0 0 0 0 ATREPM ACLRM SQCLR SQSET SQMON PBSY Bit 15 Name BSTS Buffer status Function Software Hardware Remarks W 14 13 12 11 10 9 8 7 6 5 4-2 1-0 The FIFO buffer status of the pipe is shown. R 0: Buffer access is disabled 1: Buffer access is enabled When the pipe is transmitting, the FIFO buffer status of the pipe INBUFM is shown. Sending buffer R 0: FIFO buffer contains no transmittable data monitor 1: FIFO buffer contains transmittable data CSCLR Write CSCLR=1 to clear the CSSTS bit of the pipe. R/W(1) CSPLIT status clear 0: Write invalid bit 1: Clear CSSTS bit C-Split status of split transaction of the pipe is shown. CSSTS 0: During the S-Split transaction process or transfer without using R CSSTS status bit a split transaction 1: During the C-Split transaction process Unassigned. Fix to "0". Specifies auto response is disabled/enabled for the pipe. 0: disabled ATREPM 1: enabled (irrespective of the FIFO buffer status of the pipe, a R/W Auto response mode zero-length packet response while sending, NAK response and a NRDY interrupt is issued while receiving) ACLRM Specifies auto buffer clear mode is disabled/enabled of the pipe. R/W Auto buffer clear 0: Disabled mode 1: Enabled (all buffers are initialized) Specifies "1" while clearing the expected value of the sequence SQCLR toggle bit in the next transaction of the pipe, to DATA0. R(0)/W(1) Toggle bit clear 0: Write invalid 1: Specifies DATA0 Specifies "1" while clearing the expected value of the sequence SQSET toggle bit in the next transaction of the pipe, to DATA1. R(0)/W(1) Toggle bit set 0: Write iis nvalid 1: Specifies DATA1 Sets the expected value of the sequence toggle bit in the next SQMON transaction of the pipe. R Toggle bit confirm 0: DATA0 1: DATA1 Sets whether the pipe is being used by the current USB bus. PBUSY 0: Pipe not used in the USB bus R Pipe busy 1: Pipe used in the USB bus Unassigned. Fix to "0". Specifies the response method in the next transaction of the pipe. PID 00: NAK response R/W Response PID 01: BUF response (maintaining the buffer state) 10: STALL response 11: STALL response W H (Set to "0" when P) H R/W(0) R/W R P (Set to "0" when H) R R R W W R/W Remarks None Rev1.01 Oct 17, 2008 page 96 of 183 R8A66597FP/DFP/BG 2.17.1 Buffer status bit (BSTS) This is the bit by which the controller displays whether access from the CPU to the FIFO buffer assigned to the pipe is possible. The meaning of this bit differs according to the setup value of the DIR, BFRE and DCLRM bits. Table 2.17 BSTS Bit Operations DIR Bit Setup Value 0 BFRE bit Setup Value 0 DCLRM Bit Setup Value 0 1 1 0 1 1 0 1 0 1 0 1 Meaning of BSTS bit Sets "1" "when reading of the reception data of the FIFO buffer is possible" and sets "0" when the data is read completely. This combination cannot be written. Sets "1" "when reading of the reception data of the FIFO buffer is possible" and sets "0" when the software writes "BCLR=1" after reading the data completely. Sets "1" "when reading of the reception data of the FIFO buffer is possible" and sets "0" when the data is read completely. Sets "1" "when writing of the transmission data to the FIFO buffer is possible" and sets "0" when the data is written completely. This combination cannot be written. This combination cannot be written. This combination cannot be written. 2.17.2 Sending buffer monitor bit (INBUFM) When the pipe is set to transmit ("DIR=1"), the controller sets "1" to this bit when the software (or DMAC) writes the data on at least one side in the FIFO buffer. The controller sets "0" in this bit when all the written data is transmitted from the FIFO buffer. When the double buffer is used (if "DBLB=1" is written), "0" is displayed in this bit when the controller has transmitted the data on both the sides and the software (or DMAC) has not completely written the data on one side. When the pipe is set to receive ("DIR=0"), this bit shows a value similar to the BSTS bit. 2.17.3 CSPLIT status clear of split transaction bit (CSCLR) When the Host Controller function is selected, if the software writes "1" to this bit, the controller clears the CSSTS bit to "0". In using the Split Transaction transfer, if the next transfer is restarted forcefully from the S-Split, use the software to write "1" to this bit. Normally in a Split Transaction, since the controller automatically clears the CSSTS bit to "0" when the C-Split is completed, software is not necessary for the clear process. Not modify the CSSTS bit by using this bit except when the communication is stopped by "UACT=0" or when confirmed that transfer is not complete due to detach detection. "CSSTS=0" is not modified even if writing "1" to this bit when "CSSTS=0". When the Peripheral Controller function is selected, write "0" to this bit. 2.17.4 CSPLIT status of split transaction bit (CSSTS) When the Host Controller function is selected, the controller displays the C-Split status of the Split transaction in this bit. The controller sets "1" in this bit while starting the C-Split and sets "0" in this bit when the C-Split end is detected. The setting of this bit shows the valid values only when the Host Controller function is selected. Rev1.01 Oct 17, 2008 page 97 of 183 R8A66597FP/DFP/BG 2.17.5 Auto response mode bit (ATREPM) If the Peripheral Controller function is selected, when the transfer type of thepipe is written to "BULK", "1" can be written to this bit. When "1" is written to this bit, the controller responds as shown below for the token from the USB Host. (1) If pipe of Bulk-IN transfer (write "TYPE=01" and "DIR=1") If writing "ATREPM=1" and "PID=BUF", the controller sends a zero-length packet for the token. Whenever an acknowledgement is received from the USB Host (If there is one transaction, the token received zero-length packet sent ACK received), the controller updates the sequence toggle bit (DATA-PID). BRDY and BEMP interrupts do not occur. (2) If pipe of Bulk-OUT transfer (set "TYPE=01" and "DIR=0") If writing "ATREPM=1" and "PID=BUF", the controller sends a NAK response for the OUT-token (or PING-token) and issues an NRDY interrupt. This bit can be modified when "CSSTS=0" and "PID=NAK". To modify this bit after modifying the PID bit of the pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0" and then modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. When writing "1" to this bit to execute USB communication, the FIFO buffer should be empty. While "1" is written to this bit to execute USB communication, do not write to the FIFO buffer. If the transfer type of the pipe is isochronous,write "0" to this bit. When the Host Controller function is selected, write "0" to this bit. 2.17.6 Auto buffer clear mode bit (ACLRM) To delete all content from the FIFO buffer allocated to the pipe, write "1" and "0" sequentially in the ACLRM bit. When "1" and "0" are written sequentially in this bit, the contents to be cleared by the controller and the instances when the items need to be cleared are shown in Table 2.18. Table 2.18 Contents Cleared by the Controller if writing "ACLRM=1" settings No. (1) (2) (3) (4) (5) Contents cleared by ACLRM bit operation All contents of the FIFO buffer allocated to the pipe (clear both sides of the FIFO buffer while settingto the double buffer) Interval count value, if transfer type of the pipe is isochronous Internal flag related to BFRE bit FIFO buffer toggle control Internal flag related to the transaction count Instances when clearing the contents is necessary To reset the interval count value When modifying the BFRE bit setup value When modifying the DBLB bit setup value If there is a forceful termination of transaction count function This bit can be modified when "CSSTS=0", "PID=NAK", and when the pipe in the CURPIPE bit is not written. To modify this bit after modifying the pipe PID bit from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify it. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. Rev1.01 Oct 17, 2008 page 98 of 183 R8A66597FP/DFP/BG 2.17.7 Clear bit of sequence toggle bit (SQCLR) If the software writes "1" to this bit, the controller writes the expected value of the sequence toggle bit of the pipe to DATA0. The controller always sets "0" to this bit. When the Host Controller function is selected, if "1" is written to this bit for the Bulk-Out transfer pipe, the controller starts the next transfer of the pipe from the PING-token. Not write "1" to the SQCLR bit except when "CSSTS=0" and "PID=NAK". To write "1" to this bit after the PID bit of the PIPE is modified from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0" and then modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.17.8 Write bit of sequence toggle bit (SQSET) If the software writes "1" to this bit, the controller sets the expected value sequence toggle bit of the pipe to DATA1. The controller always sets "0" to this bit. Not write "1" to the SQSET bit except when "CSSTS=0" and "PID=NAK". To write "1" to this bit after the PID bit of the PIPE is modified from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.17.9 Monitor bit of sequence toggle bit (SQMON) In this bit, the controller displays the expected value of the sequence toggle bit of the pipe. If the selected pipe other than transfer type isochronous, the controller toggles this bit if the transaction is executed normally. However, this bit is not toggled if there is a DATA-PID mismatch during reception direction transfer. 2.17.10 Pipe busy bit (PBUSY) The controller modifies this bit from "0" to "1" when the USB transaction of the pipe is started. When one transaction is completed, the bit is modified from "1" to "0". When the software has set "PID=NAK", possibility of pipe modification can be checked by reading this bit. Rev1.01 Oct 17, 2008 page 99 of 183 R8A66597FP/DFP/BG 2.17.11 Response PID bit (PID) For this bit, set a response of the controller in each pipe by the software. The default value of this bit is "NAK". While executing a USB transfer by the pipe, modify this bit to "BUF". The basic operations (operations when there is no error in the communication packet) of this controller for each setup value of the PID bit are given in Table 2.19 and Table 2.20. If the pipe is in USB communication, when this bit is modified from "BUF" to "NAK" by the software, after writing "NAK", to check whether the USB transfer of pipe is actually shifted to "NAK" status, and check whether "PBUSY=1". However, when the controller modifies this bit to "NAK", it is not necessary to use the software to check the PBUSY bit. In following cases, the controller modifies the value of this bit: (1) When the pipe is receiving and when the software has written "1" to the SHTNAK bit of the pipe, the controller sets "PID=NAK" upon identifying the transfer end. (2) For the pipe, when the data packet of payload exceeding the maximum packet size is received, the controller sets "PID=STALL(11)". (3) When the Peripheral Controller function is selected and when the USB bus reset is detected, the controller sets "PID=NAK". (4) When the Host Controller function is detected and when a reception error such as a CRC error is detected continuously three times, the controller sets "PID=NAK". (5) When the Host Controller function is selected and when a STALL handshake is received, the controller sets "PID=STALL(11)". Write "10" to shift from "PID=NAK("00")" status to "PID=STALL" status. Write "11" to shift from BUF("01") status to STALL status. First write "10" and then write "00" to shift form "STALL(11)" to NAK status. First, shift to NAK status and then to BUF status to shift from STALL status to BUF status. Rev1.01 Oct 17, 2008 page 100 of 183 R8A66597FP/DFP/BG Table 2.19 List of Controller Operations According to the PID bit (When the Host Controller function is selected) PID Bit Setup Value "00 (NAK)" Controller Operations According Transfer Controller Operations Direction (DIR Bit Setup Value) Not dependent on setup Not dependent on setup Token not issued. value value Token is issued when "UACT=1" is written, and when Bulk ("TYPE=01") Not dependent on setup the FIFO buffer of the pipe is in Send/Receive or value Enabled status. Token not issued when "UACT=0" or Interrupt ("TYPE=10") the status is other than Send/Receive Enabled. A token is issued when "UACT=1" is written, Not dependent on setup regardless of the state of the FIFO buffer that Isochronous ("TYPE=11") value corresponds to the selected PIPE. A token is not issued if "UACT=0". Transfer TYPE (TYPE Bit Setup Value) Not dependent on setup value Not dependent on setup Token not issued value "01 (BUF)" "10 (STALL)" or "11 (STALL)" Table 2.20 List of Controller Operations According to the PID bit (When the Peripheral Controller function is selected) PID Bit Setup Value "00 (NAK)" Transfer TYPE (TYPE Bit Setup Value) Bulk ("TYPE=01") or Interrupt ("TYPE=10") Isochronous ("TYPE=11") Pipe use disabled ("TYPE=00") Transfer Direction (DIR Bit Setup Value) Not dependent setup value Not dependent setup value Not dependent setup value on on on Controller Operations NAK response is sent to the token from the USB Host. However, when "ATREPM=1", operations mentioned in 2.17.5 are executed. Does not respond to the token from the USB Host Does not respond to the token from the USB Host "01 (BUF)" Bulk ("TYPE=01") Receive ("DIR=0") Interrupt ("TYPE=10") Receive ("DIR=0") Bulk ("TYPE=01") or Interrupt ("TYPE=10") Isochronous ("TYPE=11") Transmit ("DIR=1") Receive ("DIR=0") Transmit ("DIR=1") "10 (STALL)" or "11 (STALL)" Bulk ("TYPE=01") or Interrupt ("TYPE=10") Isochronous ("TYPE=11") Not dependent setup value Not dependent setup value When an OUT token is sent from the USB Host, if the FIFO buffer for the selected PIPE is in the receive-enabled state, the data is received and an ACK or NYET response is returned. If not, a NAK response is returned. When a PING token is sent from the USB Host, if the FIFO buffer of the selected PIPE is in the receive-enabled state, an ACK response is returned. If not, a NAK response is returned. For the Out-token from the USB Host, if the FIFO buffer of the pipe is in Receive Enabled status, the data is received and an ACK response is sent. Otherwise the NAK response is sent. If the corresponding FIFO buffer is in Send Possible status, the data is sent for the token from the USB. Otherwise a NAK response is sent. For the Out-token from the USB Host, if the FIFO buffer of the pipe is in Receive Enabled status, the data is received. Otherwise, the data is deleted. If the corresponding FIFO buffer is in Send Possible status, the data is sent for the token from the USB. Otherwise, a zero-length packet is sent. on A STALL response is sent to the token from the USB Host. on Does not respond to the token from the USB Host. Rev1.01 Oct 17, 2008 page 101 of 183 R8A66597FP/DFP/BG Pipe6 control register [PIPE6CTR] Pipe7 control register [PIPE7CTR] Pipe8 control register [PIPE8CTR] Pipe9 control register [PIPE9CTR] 15 14 13 12 11 BSTS 0 ? ? CSSLR CSSTS 0 0 ? ? 10 ? ? 9 8 7 6 5 4 ? ? 3 ? ? PID ? ? 0 0 0 0 ACLRM SQCLR SQSET SQMON PBSY 0 0 0 0 0 - Bit 15 14 13 Name BSTS Buffer status Unassigned. Fix to "0". CSCLR CSPLIT status clear bit Function FIFO buffer status of the pipe is displayed. 0: Buffer access is disabled 1: Buffer access is enabled Write CSCLR=1 to clear the CSSTS bit of the pipe. 0: Write disabled 1: Clear CSSTS bit C-SPLIT status of Split transaction of the pipe is displayed. 0:During S-Split Transaction process or transfer without using Split Transaction 1: During C-Split Transaction process Software Hardware Remarks R W R/W(1) R/W(0) H (Write to "0" when P) H 12 CSSTS CSSTS status bit R R/W 11-10 Unassigned. Fix to "0". Specifies auto buffer clear mode disable/enable of the pipe. ACLRM 0: Disabled Auto Buffer Clear mode 1: Enabled (all buffers are initialized) Specifies "1" while clearing the expected value of the sequence SQCLR toggle bit in the next transaction of the pipe to DATA0. 8 Toggle Bit Clear 0: Invalid 1: Specifies DATA0 Specifies "1" while clearing the expected value of the sequence SQSET toggle bit in the next transaction of the pipe to DATA1. 7 Toggle Bit Set 0: Invalid 1: Specifies DATA1 Sets the expected value of the sequence toggle bit in the next SQMON transaction of the pipe. 6 Toggle Bit Confirm 0: DATA0 1: DATA1 Displays whether the pipe is being used by the current USB PBUSY bus. 5 Pipe busy 0: Pipe not used in the USB bus 1: Pipe used in the USB bus 4-2 Unassigned. Fix to "0". Specifies the response method in the next transaction of the pipe. PID 00: NAK response 1-0 Response PID 01: BUF response (in keeping with the buffer state) 10: STALL response 11: STALL response 9 Remarks None R/ W R/W R(0)/ W(1) R R(0)/ W(1) R R W R W R/W R/W Rev1.01 Oct 17, 2008 page 102 of 183 R8A66597FP/DFP/BG 2.17.12 Buffer status bit (BSTS) Refer to 2.17.1. 2.17.13 CSPLIT status clear bit of split transaction (CSCLR) Refer to 2.17.3. 2.17.14 Split Transaction C-SPLIT status bit of split transaction (CSSTS) Refer to 2.17.4. 2.17.15 Auto buffer clear mode (ACLRM) To delete all content from the FIFO buffer allocated to the pipe, write "1" and "0" sequentially in the ACLRM bit. When "1" and "0" are written sequentially to this bit, the contents to be cleared by the controller and the cases when the items need to be cleared are shown in Table 2.21. Table 2.21 Contents cleared by the controller if writing "ACLRM=1" No. Contents cleared by ACLRM bit operation Instances when clearing the contents is necessary (1) All content from the FIFO buffer allocated to the pipe When the Host Controller function is selected, interval count (2) To reset the value of interval count value if the pipe of transfer type interrupt While modifying the BFRE bit setup value (3) Internal flag related to BFRE bit If there is a forceful termination of transaction count (4) Internal flag related to transaction count function This bit can be modified when "CSSTS=0", "PID=NAK", and the pipe in the CURPIPE bit is not written. To modify this bit after modifying the PID bit of the pipe from "BUF" to "NAK" check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.17.16 Clear bit of sequence toggle bit (SQCLR) Refer to 2.17.7. 2.17.17 Set bit of sequence toggle bit (SQSET) Refer to 2.17.8. 2.17.18 Monitor bit of sequence toggle bit (SQMON) Refer to 2.17.9. 2.17.19 Pipe busy bit (PBUSY) Refer to 2.17.10. 2.17.20 Response PID bit (PID) Refer to 2.17.11. Rev1.01 Oct 17, 2008 page 103 of 183 R8A66597FP/DFP/BG 2.18 Transaction counter Pipe1 Transaction counter enabled register [PIPE1TRE] Pipe2 Transaction counter enabled register [PIPE2TRE] Pipe3 Transaction counter enabled register [PIPE3TRE] Pipe4 Transaction counter enabled register [PIPE4TRE] Pipe5 Transaction counter enabled register [PIPE5TRE] 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? ? ? ? ? TRENB TRCLR 0 0 - 7 ? ? 6 ? ? 5 ? ? 4 ? ? 3 ? ? ? ? ? ? ? ? Bit Name Function Software Hardware Remarks 15-10 Unassigned. Fix to "0". 9 TRENB Transaction counter enabled Specifies whether the transaction counter is invalid/valid. R/W 0: Transaction counter function invalid 1: Transaction counter function valid Transaction counter can be cleared to "0" by writing "1" to this bit. R(0)/W(1) 0: Invalid 1: Count counter clear R 8 TRCLR Transaction counter clear R 7-0 Unassigned. Fix to "0"." Remarks * Not modify each bit of the register except when "CSSTS=0" and "PID=NAK". To modify each bit after modifying the PID bit of the pipe from "BUF" to "NAK", check that "CSSTS=0" and "PBUSY=0", and then modify it. However, when the controller modifies PID bit to "NAK", it is not necessary to check the PBUSY bit. 2.18.1 Transaction counter enabled bit (TRENB) For the reception pipe, after the total number of packets is written to the TRNCNT bit using the software, the controller executes the following control on receiving the same number of packets as the setup value of the TRNCNT bit: (1) When the continuous transmission/reception mode is used (write "CNTMD=1"), toggles on CPU side even if the FIFO buffer is not full when reception is completed. (2) If writing "SHTNAK=1", modifies the pipe PID bit to "NAK". (3) If writing "DENDE=1" and "PKTMD=0", asserts the DEND signal while reading the last data. (4) If writing "BFRE=1", asserts the BRDY interrupt. Regarding the transmission pipe, write "0" to this bit. When the transaction count function is not used, write "0" to this bit. When the transaction count function is used, set the TRNCNT bit before writing "1" to this bit. Also write "1" to this bit before receiving the initial packet that is the transaction target. 2.18.2 Transaction counter clear bit (TRCLR) If the software writes "1" to this bit, the controller clears the current count value of the transaction counter corresponding to the pipe and sets "0" in this bit. Rev1.01 Oct 17, 2008 page 104 of 183 R8A66597FP/DFP/BG Pipe1 transaction counter register [PIPE1TRN] Pipe2 transaction counter register [PIPE2TRN] Pipe3 transaction counter register [PIPE3TRN Pipe4 transaction counter register [PIPE4TRN] Pipe5 transaction counter register [PIPE5TRN] 15 14 13 12 11 10 0 Bit 0 0 Name 0 0 0 - 9 0 - 8 7 TRNCNT 0 0 Function 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - Software Hardware Remarks 15-0 TRNCNT Transaction counter Transaction counter If Write: Specifies the total number of reception packets (number of transactions) to be received by the selected PIPE. If Read: If "TRENB=0": Displays the written transaction counter If "TRENB=1": Displays the transaction counter during the count R/W R/W Remarks 2.18.3 Transaction counter bit (TRNCNT) For the reception pipe, after the total number of packets is written to this bit using the software, if "1" is written to the TRENB bit, the controller executes the control mentioned in 2.18.1. If "TRENB=0", the controller shows the number of transaction written by the software to this bit. If "TRENB=1", the controller shows the number of transaction in the count in this bit. The controller increases the TRNCNT bit by one, when the following conditions are fulfilled in the status at the time of reception: (a) "TRENB=1" (b) (TRCNT written value current number of transaction +1) while receiving the packet (c) The payload of the received packet matches the written value of the MXPS bit When the controller fulfills one of the following conditions ((1) - (3)), the TRNCNT bit is cleared to "0". (1) When all the following conditions are fulfilled: (a) "TRENB=1" (b) While receiving the packet (TRCNT setup value = current value +1) (c) The payload of the received packet matches with the setup value of MXPS bit (2) When both of the following conditions are fulfilled: (a) "TRENB=1" (b) A short packet is received (3) When both of the following conditions are fulfilled: (a) "TRENB=1" (b) When the software writes "1" to the TRCLR bit For the transmission pipe, write "0" to this bit. When the transaction count function is not used, write "0" to this bit. This bit can be modified when "CSSTS=0", "PID=NAK" and "TRENB=0". To modify this bit after modifying the pipe PID bit from "BUF" to "NAK" check that "CSSTS=0" and "PBUSY=0", and modify the bit. However, when the controller has modified the PID bit to "NAK", it is not necessary to check the PBUSY bit. When modifying the bit value, write "TRCLR=1" before writing "TRENB=1". Rev1.01 Oct 17, 2008 page 105 of 183 R8A66597FP/DFP/BG 2.19 Device Address Configuration Register Device Address0 configuration register [DEVADD0] Device Address1 configuration register [DEVADD1] Device Address2 configuration register [DEVADD2] Device Address3 configuration register [DEVADD3] Device Address4 configuration register [DEVADD4] Device Address5 configuration register [DEVADD5] Device Address6 configuration register [DEVADD6] Device Address7 configuration register [DEVADD7] Device Address8 configuration register [DEVADD8] Device Address9 configuration register [DEVADD9] Device AddressA configuration register [DEVADDA] 15 14 13 12 11 10 9 8 UPPHUB HUBPORT ? 0 0 0 0 0 0 0 ? Bit 15 Name Unassigned. Fix to "0". H (Write all "0" when P) H (Write all "0" when P)" Function 7 6 USBSPD 0 0 - 5 ? ? 4 ? ? 3 ? ? 2 ? ? Software Hardware Writes the USB address of the HUB to which the UPPHUB communication target Peripheral device is connected. 14-11 Communication target 0000: Directly connected to the port of the controller. connected HUB register 0001-1010: USB address of HUB 1011-1111: Reserved Writes the port number of the HUB to which the HUBPORT communication target Peripheral device is connected. 10-8 Communication target 000: Directly connected to the controller port. connected HUB port 001-111: Port number of HUB Writes the USB transfer speed of the Peripheral device of the USBSPD communication target. Transfer speed of 00: DEVADDx register not used 7-6 communication target 01: Low-Speed device 10: Full-Speed 11: Hi-Speed 7-1 Unassigned. Fix to "0". Writes the port number (root hub port number) of the RTPORT controller to which the communication target tool is Root hub port number 0 connected. of the communication 0: Port0 target tree 1: Port1 R/W R R/W R R/W R H (Write all "0" when P)" R/W R H (Write all "0" when P)" Remarks *1. When the Host Controller function is selected, write to each bit of the register before starting communication related to each pipe. *2. Only modify the bits of this register if there are no valid pipes using the settings of the bit to be changed.. A valid pipe is the one that fulfills the following conditions: (a) When the DEVSEL bit settings specify this register (b) When "BUF" is written to the PID bit of the pipe, or when the pipe is DCP and is written to "SUREQ=1" *3. When the Peripheral Controller function is selected, write "0" to each bit of this register. Rev1.01 Oct 17, 2008 page 106 of 183 R8A66597FP/DFP/BG 2.19.1 Communication target connected HUB register bit (UPPHUB) When the Host Controller function is selected, the controller generates a packet by referring the set value of this bit while executing a Split transaction. 2.19.2 Communication target connected HUB port bit (HUBPORT) When the Host Controller function is selected, the controller generates a packet by referring the set value of this bit while executing a Split transaction. 2.19.3 Transfer speed of communication device bit (USBSPD) When the Host Controller function is selected, the controller generates a packet by referring the set value of this bit. 2.19.4 Root hub port number of communication target tree bit (RTPORT) When the Host Controller function is selected, the controller generates a packet by referring the set value of this bit. Rev1.01 Oct 17, 2008 page 107 of 183 R8A66597FP/DFP/BG 3 Operating Instructions 3.1 System Controls and Oscillation Controls This chapter provides instructions concerning register operations necessary to initialize the R8A66597 controller and descriptions of the registers necessary to control power consumption. 3.1.1 RESET Table 3.1 shows the list of the various resets related to this controller. Please refer to "Chapter 2. Registers" for a description of the register initialization status after each reset operation. Table 3.1 RESET List Name H/W Reset USB Bus Reset Operation "L" level input from RST_N pin When Peripheral Controller function is selected, controller detects reset automatically from D+/D- line status 3.1.2 Bus Interface Setting Table 3.2 shows the parameters for the controller bus interface that must be set before enabling ("XCKE = 0") the oscillation buffer operation. Make sure these are set immediately after the H/W reset. Table 3.3 shows the parameters to be set after the oscillation buffer operation is enabled ("XCKE = 1" is set and controller is in "SCKE = 1" status). Table 3.2 Bus Interface Settings (set before clock supply starts) Register Name PINCFG PINCFG Bit Name LDRV INTA Setting Description Specify drive current controls Set INT_N pin polarity Table 3.3 Bus Interface Settings (set after clock supply starts) Register Name SYSCFG1 SYSCFG1 DMAxCFG DMAxCFG DMAxCFG DMAxCFG SOFCFG SOFCFG x = 0 or 1 Bit Name PCSDIS LPSME DREQA DACKA DENDA OBUS BRDYM INTL Setting Description Specify include/exclude CS_N assert in recovery conditions from low power sleep state Specify enable/disable for low power sleep state Set DREQx_N pin polarity Set DACKx_N pin polarity Set DENDx_N pin polarity Set OBUS mode Set PIPEBRDY interrupt status clear timing Set INT_N pin output sense 3.1.3 Clock Supply Control The clock supply to the controller USB block is started by selecting the XIN pin input clock in the SYSCFG register XTAL bit and enabling the oscillation buffer in the XCKE bit by software. Confirm by software that the SCKE bit is set to "1", then proceed with the next process. Rev1.01 Oct 17, 2008 page 108 of 183 R8A66597FP/DFP/BG 3.1.4 USB Block Operation Enable After clock supply has started to the USB block ("SCKE = 1"), set the SYSCFG register USBE bit to "1" with software to enable USB block operations. 3.1.5 Controller Function Selection Bit Setting After enabling the USB block operations, set the controller function selection bit (SYSCFG register DCFM bit). Use software to select either the Host Controller function or the Peripheral Controller function. Table 3.4 shows the function selections for each USB port on the controller. Table 3.4 USB Port Function Selections When Host Controller function is selected ("DCFM = 1") No. PORT0 PORT1 Scheduling for each port (1) Hi-Speed Hi-Speed Transfer scheduling is shared between PORT0 and PORT1 and the output is driven to both ports. (2) Full or Low Full or Low (3) Hi-Speed Full or Low Transfer scheduling is operated separately for PORT0/PORT1 and is not dependent on the transfer speed (4) Full or Low Hi-Speed of each port. When Peripheral Controller function is selected ("DCFM = 0") PORT0 PORT1 Notes (5) Hi or Full unused PORT1 is invalid. Low-Speed is not supported. 3.1.6 Hi-Speed Operation Enable Bit Setting and USB Transmission Speed Determination 3.1.6.1 When Host Controller function is selected When the Host Controller function is selected, set the Hi-Speed operation enable bit (PORT0: SYSCFG register HSE bit, PORT1: SYSCFG1 register HSE bit) to "1" only after attachment of Peripheral device is detected and the D+ line of the attached device is pulled up (i.e. not in Low-Speed mode). If the attached device is Low-Speed, or if Hi-Speed operation is not enabled, set the Hi-Speed operation enable bit of the corresponding PORT to "0". In addition, if the attached device is Low-Speed, the SOFCFG register TRNENSEL bit must be set to "1". See Chapter 3.6.1 for more details. When a USB reset is issued ("USBRST = 1") to a PORT which is enabled for Hi-Speed operation, the controller will execute the Reset Handshake Protocol and automatically determine the USB transmission speed. The result of the PORT0 Reset Handshake is displayed in the DVSTCTR1 register RHST bit and the PORT1 result in DVSTCTR1 register RHST bit. 3.1.6.2 When Peripheral Controller Function is selected When the Peripheral Controller function is selected and Hi-Speed operation is enabled, set the Hi-Speed operation enable bit (SYSCFG register HSE bit) to "1" after setting the controller function selection bit. If operating the controller only at Full-Speed, set the SYSCFG register HSE bit to"0". When Hi-Speed operation is enabled, the controller executes the reset handshake protocol and automatically determines the USB transmission speed. The result of the reset handshake is shown in the DVSTCTR0 register RHST bit. Rev1.01 Oct 17, 2008 page 109 of 183 R8A66597FP/DFP/BG 3.1.7 DCFM Bit Setup Values and USB Transmission Speed Control Table 3.5 shows the DCFM bit setup values and the corresponding USB transmission speeds. Table 3.5 Controller Function Selection Table DCFM 0 0 Settings PORT0 HSE 0 1 PORT1 HSE 0 0 Controller Function Peripheral Function and Transmission speed PORT1 Remarks Speed PORT1 PORT0 operates at Full-Speed invalid Hi or Full PORT1 The PORT0 operates at Hi-Speed when Reset invalid Handshake Protocol (RHSP) is successful, at Full-Speed when RSHP is not successful. Full or Full or PORT0 and PORT1 operate at Full-Speed when D+ is Low Low pulled up, Low-Speed when D- is pulled up. When D- is pulled up, make sure to set "HSE=0" in the corresponding port. Hi or Full Full or PORT0: The port operates as a Hi-Speed Host Low Controller when RHSP is successful; Full-Speed when RHSP is not successful. PORT1: The port operates at Full-Speed when D+ is pulled up, Low-Speed when D- is pulled up. When D- is pulled up, make sure to set "HSE=0" in the corresponding port. Full or Hi or Full PORT0: The port operates at Full-Speed when D+ is Low pulled up, Low-Speed when D- is pulled up. When D- is pulled up, make sure to set "HSE=0" in the corresponding port. PORT1: The port operates Hi-Speed Host Controller when RHSP is successful. When RHSP is not successful, the port operates at Full-Speed. Hi or Full Hi or Full PORT0 or PORT1 operates as Hi-Speed Host Controller when RHSP is successful. When RHSP is not successful, either port operates at Full-Speed. PORT0 Speed Full 1 0 0 Host 1 1 0 1 0 1 1 1 1 Rev1.01 Oct 17, 2008 page 110 of 183 R8A66597FP/DFP/BG 3.1.8 USB Data Bus Pull-Down and Pull-Up Settings After selecting the controller function, set the resistance for the USB data line. This controller has built-in pull-up resistance for the D+ line and pull-down resistance for both the D+ and D- lines. Power supply for the D+ pull-up is AVCC. When the Host Controller function is selected, set SYSCFG register DRPD bit to "1" if using PORT0 and set SYSCFG1 register DRPD bit to "1" if using PORT1, and pull-down the D+ and D- lines for each port. When the Peripheral Controller function is selected, after the connection to the USB Host is confirmed, set SYSCFG register DPRPU bit to "1" and pull-up D+. In addition, the controller has built-in D+/D- line terminating resistance for Hi-Speed transmissions and output resistance for Full-Speed transmissions. The controller automatically switches the built-in resistance after connection to the USB Host or Peripheral device upon the execution or detection of a reset handshake, suspend, or resume event. When the Peripheral Controller function is selected and the SYSCFG register DPRPU bit is set to "0" in the USB Host attached status, the controller disables the USB D+ line pull-up (or D+, D- line termination). Therefore, software can be used to create the USB cable detached status when viewed from the USB Host. Rev1.01 Oct 17, 2008 page 111 of 183 R8A66597FP/DFP/BG 3.1.9 Power-Consumption Control 3.1.9.1 Power Consumption Control Outline The R8A66597 controller offers two types of low-consumption power supply: Low Power Sleep State and Vcc-OFF State. Table 3.6 provides a description of each low-power consumption state. Figure 3.1 shows a diagram of the controller status transitions. Table 3.6 Low Power Consumption States Controller State Low Power Sleep State Description The controller transitions to the low-power sleep state when "LPSME=1" is set during initialization, and the clock is stopped in the current controller operation state (refer to 3.1.10.2). The value of each register is maintained, but the contents of the FIFO buffer are not saved. The controller can be transitioned to the Vcc-OFF state by turning off only Vcc while keeping VIF on. This state reduces power consumption even further than that of the low-power sleep state. The values in the registers are not saved. Vcc-OFF State VCC, AVCC, VIF on H/W Reset Initialized state after H/W reset Initialization (when "a ttach" etc. is detected) Stop clock sequence completed Recovery event *1) Normal operating state VCC or AVCC off (VIF remains on) VCC, AVCC on VCC OFF state Low-power sleep state Only VCC off (VIF remains ON) 1) Recovery Event: CS_N signal is asserted by CPU dummy read when "PCSDIS=1" or detection of RESM interrupt when "RSME=1", or detection of VBINT interrupt when "VBSE=1", or detection of BCHG interrupt when "BCHGE=1". Figure 3.1 Controller State Transition Diagram Rev1.01 Oct 17, 2008 page 112 of 183 R8A66597FP/DFP/BG 3.1.9.2 Low-Power Sleep State When SYSCFG1 register LPSME bit is set to "1" in the controller initialization, if the clock stop process is executed while the controller is in the normal operating state, the controller goes to the low-power sleep state. In this state, power consumption is reduced while maintaining the value of each register. If the controller is transitioned to this state during USB suspend, power consumption can be reduced while still maintaining the USB address, device state, and other information. Please refer to 3.1.10.2 and Figure 3.3 for the detailed the setup sequence to transition to the low-power sleep state. To return from the low-power sleep state, refer to Table 2.7. The return sequence is detailed in 3.1.10.3 and Figure 3.4. The controller automatically enables the oscillation buffer operation when it detects a recovery condition from the low-power sleep state. At this time, the value of the XCKE bit is not changed. The user must confirm "SCKE=1" by software and then set "XCKE=1". To enable the low-power sleep state, set the SYSCFG1 register LPSME bit to "1" during controller initialization. Registers cannot be accessed during the low-power sleep state. In addition, data in the FIFO buffers will be lost during the transition, so make a send/receive data process is executed before transitioning to the low-power sleep state. When the Host Controller function is selected and a remote wakeup signal is received in the suspend state, the internal clock must be supplied within 1ms of the signal detection and the resume signal output started. Therefore, do not stop the internal clock when the controller is in the suspend state and the remote wakeup is enabled. 3.1.9.3 VCC OFF State The VCC OFF state allows some power to be supplied to the controller but cuts off supply to the USB block. The controller is transitioned to the VCC OFF state by keeping the VIF on while turning off the VCC and AVCC. Unlike returning the controller from the low-power sleep state by controlling the registers with software, this state requires the VCC and AVCC to be turned on and an H/W reset executed. The contents of each register are lost when the VCC is turned off, and the controller goes to the initialization state after recovery. Rev1.01 Oct 17, 2008 page 113 of 183 R8A66597FP/DFP/BG 3.1.10 State Transition Timing 3.1.10.1 Start of Internal Clock Supply (from H/W reset state to normal operating state) Figure 3.2 shows a diagram of the clock supply start control timing for the controller. When transitioning from the H/W reset state or the clock stopped state to the normal operating state, handle the bits according to the timing below. (1) Enable oscillation buffer "XCKE=1" (2) Software wait until "SCKE=1". (Controller automatically enables PLLC and SCKE.) Start internal clock supply start process XCKE (1) (2) PLLC(H/W) SCKE(H/W) Figure 3.2 Clock Supply Start Control Timing Diagram 3.1.10.2 Internal Clock Supply Stop (setup sequence to transition from normal operating state to low -power sleep state) Figure 3.3 shows the control timing diagram for transitioning the controller from the normal operating state to the low-power sleep state. To enable the low-power sleep state, set "LPSME=1" in the initialization. (1) Confirm SOFCFG register EDGESTS bit, then use software wait until "EDGESTS=0". (2) Stop internal clock supply "SCKE=0" (3) Software wait until internal clock stops. (requires 60ns or more wait) (4) Stop PLL. "PLLC=0" (5) Stop oscillation buffer operation "XCKE=0" Start XCKE PLLC SCKE (2) (3) min 60ns (4) (5) Figure 3.3 Internal Clock Supply Stop Process Timing Diagram Rev1.01 Oct 17, 2008 page 114 of 183 R8A66597FP/DFP/BG 3.1.10.3 Restart Internal Clock Supply (from low-power sleep state to normal operating state) Figure 3.4 shows a diagram for transition from the low-power sleep state to the normal operating state. (1) Interrupt is generated to trigger recovery from low-power sleep state, INT_N pin is asserted. (or, a dummy is executed by software and the controller is returned to the normal state *3)). Oscillation buffer is enabled but does not affect the XCKE bit. (2) Software wait for 1ms. (Do not access the controller during this time.) (3) Software wait until "SCKE=1". (Controller automatically starts the oscillation buffer and enables PLLC and SCKE.) (4) Set "XCKE=1" with software. *3) Return from the low-power sleep state can be enabled by accessing the CPU if SYSCFG1 register PCSDIS bit is set to "0". If returning to the normal state in these conditions, INT_N is not asserted. Generating return event from low-power sleep state XCKE PLLC(H/W) SCKE(H/W) INT_N(H/W) Event (2) (1) Values read during low-power sleep state are indeterminate. (3) (4) Figure 3.4 Control Timing Diagram for Returning from Low-Power Sleep State Rev1.01 Oct 17, 2008 page 115 of 183 R8A66597FP/DFP/BG 3.2 Interrupt Functions 3.2.1 Interrupt Function Outline Table 3.7 shows a list of controller interrupt functions. Table 3.7 Interrupt Function List Bit VBINT Interrupt Name Vbus interrupt Interrupt Detection Conditions [Usage Instructions] When change in VBUS input pin status is detected (Low to High or High to Low): [Detects Host connect/disconnect when Peripheral Controller function is selected.] When change in USB bus is detected in suspend state (J-State to K-State, J-State to SEO state): [Detects resume when Peripheral Controller function is selected.] When SOF packet with different frame number is sent When transition in device state is detected: Detects USB bus reset Detects suspend state Receives Set Address request Receives Set Configuration request When transition in control transfer stage is detected: Completes setup stage Transitions to control write transfer status stage Transitions to control read transfer status stage Completes control transfer Generates control transfer sequence error When all data in buffer memory is sent and buffer is empty When a packet is received that is bigger than maxpacket size Function Setup Host, Peripheral Related Status VBSTS Reference 2.11.1 RESM Resume interrupt Frame number update interrupt Device state transition interrupt Peripheral - 2.11.2 SOFR DVST Host, Peripheral Peripheral DVSQ 2.11.3 3.2.8 2.11.4 3.2.6 CTRT Control transfer stage transition interrupt Peripheral CTSQ 2.11.5 3.2.7 BEMP Buffer empty interrupt Buffer not ready interrupt Host, Peripheral Host, Peripheral PIPEBEMP NRDY PIPENRDY 2.11.6 2.11.23 3.2.5 2.11.7 2.11.22 3.2.4 BRDY Buffer ready interrupt OVRCR generation interrupt Host, Peripheral Host, Peripheral PIPEBRDY OVRCR BCHG Bus change interrupt Detach detection Attach detection Eor error detection interrupt Setup transaction error interrupt Setup transaction normal response interrupt DTCH When OCVMON bit of related port changes state [When Host Controller Function is selected, use to connect each of OVCR0A, OVCR0B and OVCR1 pins to overcurrent status indicated pins of VBUS supply power switch, and use to detect overcurrent for each port] When USB bus state change is detected: [When Host Controller Function is selected, use to detach ports in suspend status and detect remote wakeup] When Peripheral Device detach is detected OVCMON 2.11.8 2.11.21 3.2.3 2.11.9 2.11.16 Host, Peripheral Host - 2.11.10 2.11.17 2.11.11 2.11.18 2.11.12 2.11.19 2.11.13 2.11.20 2.11.14 - ATTCH When Peripheral Device attach is detected Host - EOFERR When EOF error is detected on corresponding port Host - SIGN When setup transaction error (no response, ACK packet corrupted) is detected When normal response (ACK) is received for setup transaction Host - SACK Host - 2.11.15 Rev1.01 Oct 17, 2008 page 116 of 183 R8A66597FP/DFP/BG Table 3.8 shows the controller INT_N pin operation. If various interrupt factors are generated, the INT_N pin output method can be set through the SOFCFG register INTL bit. Also, the INT_N pin active state can be set by the PINCFG register INTA bit. Set the INT_N operation to meet user system specifications. Table 3.8 INT_N Pin Operation INT_N Pin Operation For one type of interrupt factor Asserted until interrupt factor is released (interrupt status is cleared or interrupt enable bit is set to "disabled"). Asserted until interrupt factor is released. For various types of interrupts factors Negated for 32 clock period at 48MHz when one interrupt factor is released. Asserted until all interrupt factors are released. INTL Setting Edge Sense ("INTL=0") Level Sense ("INTL=1") Active Level: low when "INTA=0", high when "INTA=1" (1) Edge Sense Generate factor 1 Interrupt factor 1 Generate factor 2 Clear factor 1 Clear factor 2 Interrupt factor 2 NT_N Pin Negate period 1 (2) Level Sense Generate factor 1 Interrupt factor 1 Generate factor 2 Clear factor 1 Clear factor 2 Interrupt factor 2 NT_N Pin *1) When factor 1 interrupt enable bit is disabled instead of factor 1 being cleared, the negate period is not generated. Figure 3.5 INT_N Pin Operating Diagram (example when "INTA=0" is set) Rev1.01 Oct 17, 2008 page 117 of 183 R8A66597FP/DFP/BG Figure 3.6 shows the interrupt configurations for the controller.. INTENB0 VBSE INTSTS0 VBINT Detect USB bus reset Detect Set_Address Detect Set_Co nfiguration Detect Suspe nd Contro l Write Data Stage Contro l Re ad Data Stage Contro l Transfer End Contro l Transfer Error Co ntro l Transfer Setup R eceive BEMP Inte rrupt Enable Register INT_N RSME Edge / Level generated circuit RESM SOFE SOFR DVSE DVST CTRE CTRT BEMPE BEMP NRDYE NRDY BRDYE BRDY OVRC RE b9 OVRCR ... b1 b0 BEMP interrupt Status R egiste r BCHGE BCHG DTCHE DTCH ATTCHE b9 ... ... b1 ATTCH EOFE RRE EOFERR b0 NRDY Interrupt Enable R egister b9 ... b1 b0 SIGNE SIGN SACKE NRDY Interrupt Status Register b9 SACK ... ... b1 OVRCR INTENB1 OVRCRE INTSTS1 b0 BRDY Interrupt Enable R egister b9 DTCH ATTCHE BCHGE BCHG DTCHE ... b1 b0 BRDY Interrupt Status R egiste r b9 ATTCH ... ... E OFERR EOFE RRE b1 b0 INTENB2 INTSTS2 Figure 3.6 Interrupt Configuration Diagram Rev1.01 Oct 17, 2008 page 118 of 183 R8A66597FP/DFP/BG 3.2.2 Operations and Cautions for Clock Stopped State VBINT, RESM, and BCHG interrupt factors will be generated even when the clock is stopped (including low-power sleep state) and, when enabled in the interrupt enable register, the interrupt from the INT_N pin will be asserted. Clear the interrupt factors after executing the clock supply start process. When a BCHG interrupt is generated due to the Peripheral Device attach/detach while the clock is stopped, either the ATCH interrupt or the DTCH interrupt will be generated after the clock is re-started. Therefore, the attach/detach process may be executed due to the ATCH interrupt or the DTCH interrupt rather than the BCHG interrupt, depending on the determined order of interrupt factors and software process speed. 3.2.3 BRDY Interrupt The BRDY interrupt is generated when either the Host or Peripheral function has been selected. Interrupt generation conditions are as shown in listed in 2.11.21. Figure 3.7 provides the BRDY interrupt generation timing diagram. When a zero-length packet is received, the corresponding bit of the BRDYSTS register goes to "1" but the data of the corresponding packet cannot be read. Clear the buffer ("BCLR=1") after clearing the BRDYSTS register. In addition, interrupts can be generated in transfer units in PIPE1 to PIPE9 when using DMA transfers in the read direction by setting the PIPECFG register BFRE bit to "1". (1) Example of zero-length packet receive or data packet receive when BFRE=0 (single buffer setting) USB Bus Token Packet Zero-Length Packet / Short Data Packet / Data Packet (Maximum size) ACK Handshake *1) FIFO buffer status BRDY Interrupt (Change in corresponding PIPEBRDY bit) Receive-enabled state Read-enabled state *2 Buffer memory is read enabled and BDRY interrupt is generated (2) Data packet receive when BFRE=1 (single buffer setting) USB Bus Token Packet Zero-Length Packet / Short Data Packet / Data Packet (Maximum size) ACK Handshake *1) FIFO buffer status BRDY Interrupt (Change in corresponding PIPEBRDY bit) Receive-enabled state Read enabled state Buffer m emory is read enabled *2 Transfer is completed and BRDY interrupt is generated *3 (3) Example of packet send (single buffer setting) USB Bus FIFO buffer status BRDY Interrupt (Change in corresponding PIPEBRDY bit) Token Packet Send-enabled state Data Packet ACK Handshake *1) Write-enabled state Buffer memory is read enabled and BDRY interrupt is generated Packet sent by Peripheral Packet sent by Host *1) ACK Handshake is not existing in iso chro no us transfers *2) Conditions fo r FIFO buffer to be read-e nabled: One o f the following read events is generated when no unread data remains in the CPU buffer memory (1) 1 packet receive d in no n-continuo us transfer mo de, or (2) one of the following receive e vents i n the co ntinuo us transfer mode (a) receive short packet (incl. zero-le ngth) (b) buffer full o ccurs (c) re ceive packets equa l to number of packets in transactio n co unter *3) Transfer co mplete co nditio ns: W hen one of the followi ng receive events occurs (1) receive short packet (i ncl. zero-leng th), or (2) receive packets equal to number o f packets in transaction counter Figure 3.7 BRDY Interrupt Generation Timing Diagram Rev1.01 Oct 17, 2008 page 119 of 183 R8A66597FP/DFP/BG The conditions needed for the controller to clear the INTSTS0 register BRDY bit vary depending on the set value of the SOFCFG register BRDYM bit. Table 3.9 shows the conditions needed to clear the BRDY bit. Table 3.9 Conditions for BRDY Clear by Controller BRDYM BRDY Bit Clear Conditions When all bits of the BRDYSTS register are cleared by software, the controller clears the INTSTS0 0 register BRDY bit. When the BSTS bit of all pipes go to "0", the controller clears the INTSTS0 register BRDY bit. 1 Rev1.01 Oct 17, 2008 page 120 of 183 R8A66597FP/DFP/BG 3.2.4 NRDY Interrupt The NRDY interrupt is generated when either the Host or Peripheral function is selected. The conditions under which the NRDY interrupt is requested are shown in 2.11.22. Figure 3.8 shows the diagram of the NRDY interrupt generation timing for the Peripheral Controller function. (1) Data Send Example (single buffer setting) USB Bus Buffer memory status NRDY Interrupt (Change in corresponding *2 PIPENRDY bit) (2) Data Receive; OUT Token Receive Example (single buffer setting) USB Bus Buffer memory status NRDY Interrupt (Change in corresponding *2 PIPENRDY bit) (CRC bit, etc) *3 IN Token Packet NAK Handshake ( *1 Write-enabled status (no send-enabled data) OUT Token Packet Data Packet NAK Handshake (*1 Read-enabled status (no receive-enabled area) (3) Data Receive; PING Token Receive Example (single buffer setting) USB Bus Buffer memory status NRDY Interrupt (Change in corresponding PIPENRDY bit) *2 Packet sent by Host Packet sent by Peripheral *1) Handshake is not existi ng i n isochro nous transfers. *2) PIPENRDY bit is o nly changed to "1" whe n target pipe PID bit is set to "1". *3) CRC bit and OVRUN bit a re changed o nly when target pipe transfer type is iso chro nous. PING Packet NAK Handshake Read-enabled status (no receive-enabled area) Figure 3.8 NRDY Interrupt Generation Timing for Peripheral Controller Function Rev1.01 Oct 17, 2008 page 121 of 183 R8A66597FP/DFP/BG 3.2.5 BEMP Interrupt The BEMP interrupt is generated when either the Host or Peripheral function has been selected. The conditions under which the BEMP interrupt is requested are shown in 2.11.23. Figure 3.9 provides the BEMP interrupt generation timing diagram. (1) Data Send Example (*1 USB Bus Buffer memory status BEMP Interrupt (Change in corresponding PIPEBEMP bit) (2) Data Receive Example USB Bus BEMP Interrupt (Change in corresponding PIPEBEMP bit) Packet sent by Host Packet sent by Peripheral IN Token Packet Send-enabled status Data Packet ACK Handshake Write-enabled status (no send-enabled data) OUT Token Packet Data Packet (Maximum packet size over) STALL Handshake (*1 *1) Handshake is not existing in iso chrono us transfers. Figure 3.9 BEMP Interrupt Generation Timing Diagram for Peripheral Controller Function Rev1.01 Oct 17, 2008 page 122 of 183 R8A66597FP/DFP/BG 3.2.6 Device State Transition Interrupt Figure 3.10 provides a diagram of R8A66597device state transitions. The controller manages the device state and generates the device state transition interrupt. However, return from the suspend state (resume signal detection) is detected by the resume interrupt. The device state transition interrupt can be enabled or disabled by setting the INTENB0 register. The device state transition can be confirmed using the INTSTS0 register DVSQ bit. When transitioning to the default state, the device state transition interrupt is generated after the Reset Handshake Protocol is completed. Device state management is only performed when the Peripheral Controller function is selected. In the same manner, the device state transition interrupt is only generated when the Peripheral Controller function is selected. Detect suspend (DVS T='1') Powered state (DVSQ="000") Suspended state (DVSQ="100") Resume (RES M='1') Detec t US B bus reset (DV ST= '1') Detect USB bus reset (DVST='1') Detect s us pend (DVST='1') Default state (DVSQ="001") Suspended state (DVSQ="101") Resume (RESM= "1") Exec ute SetAddress (A ddress =0) (DVST='1') E xecute S etAddress (Address>0) (DVST='1') Detec t s uspend (DVST='1') Address state (DVSQ="010") Suspended state (DVSQ="110") Res ume (RES M='1') E xecute S etConfiguration (ConfigurationValue= 0) (DVS T='1') Ex ec ute SetConfiguration (ConfigurationValue?0) Detec t s uspend (DVST='1') Configured state (DVSQ="011") Suspended state (DVSQ="111") Res ume (RES M='1') Note: S olid line trans itions indicate the DV ST bit will be set to "1". Dotted line transitions indicate the RES M bit will be set to "1". Figure 3.10 Device State Transitions Rev1.01 Oct 17, 2008 page 123 of 183 R8A66597FP/DFP/BG 3.2.7 Control Transfer Stage Transition Interrupt Figure 3.11 shows a diagram of the control transfer stage transition. The controller manages the control transfer sequence and generates the control transfer stage transition interrupt. The control transfer stage transition interrupts can be enabled or disabled individually in the INTENB0 register. The transitioned transfer stage can be confirmed in the INTSTS0 register CTSQ bit. The control transfer stage transition interrupt is only generated when the Peripheral Controller function is selected. The control transfer sequence is as follows. When an error occurs, the DCPCTR register PID bit goes to "1X" (STALL). (1) Control Read Transfer (a) OUT or PING token is received before any data transfer occurs corresponding to the data stage IN token (b) IN token is received in the status stage (c) The data packet received in the status stage is a "DATAPID=DATA0" packet (2) Control Write Transfer (a) IN token is received before any ACK response is sent corresponding to a data stage OUT token (b) The first data packet received in the data stage is a "DATAPID=DATA0" packet (c) OUT or PING token is received in the status stage (3) No-Data Control Transfer (a) OUT or PING token is received in the status stage Note that in the control write transfer data stage, if the number of receive data is more than the USB request wLength value, the control transfer sequence error cannot be recognized. Also, in the control read transfer status stage, when a packet other than a zero-length packet is received, an ACK response is returned and the transfer is successfully completed. When a CTRT interrupt ("SERR=1" setting) is generated due to a sequence error, "CTSQ=110" value is stored until "CTRT=0" is written by software (interrupt status clear). Therefore, because "CTSQ=110" is being maintained, the CTRT interrupt for the completion of the setup stage is not generated, even when a new USB request is received. Events occurring after the setup stage are saved by the controller and the setup stage end interrupt is generated after the interrupt status is cleared by software. Receive setup token Receive setup token "CTSQ = 110" Control transfer 5 Detect error sequence error Receive setup token When all stages within box detect errors, the received setup token is valid. "CTSQ = 000" Setup stage Send ACK "CTSQ = 001" 1 Control read data stage OUT token "CTSQ = 010" 2 Control read status stage Send ACK 4 "CTSQ = 000" Idle stage 4 Send ACK "CTSQ = 011" 1 Control write data stage In token "CTSQ = 100" Receive ACK 3 Control write status stage "CTSQ = 101" No-data control status stage Send ACK 1 Receive ACK CTRT Interrupt 1Setup stage end 2Control read transfer status stage transition 3Control write transfer status stage transition 3Control transfer complete 5Control transfer sequence error Figure 3.11 Figure 3.11 Control Transfer Stage Transition Rev1.01 Oct 17, 2008 page 124 of 183 R8A66597FP/DFP/BG 3.2.8 Frame Number Update Interrupt Figure 3.12 shows an example of the R8A66597 SOFR interrupt output timing. In the Peripheral Controller function, when the controller detects a new SOF packet in Full-Speed operation, it updates the frame number and generates an SOFR interrupt. In Hi-Speed operation, when an SOF packet with a different frame number is detected after the controller goes to the SOF lock state, the controller updates the FRNM bit and generates the SOFR interrupt. The SOF interpolation function also runs in Hi-Speed operation after going to the SOF locked state. The SOF locked state means that two SOF packets with different frame numbers are received without errors. The SOF lock monitor start and stop conditions are as follows. (1) SOF lock monitor start conditions "USBE=1" and internal clock is supplied (2) SOF lock monitor stop conditions "USBE=0", USB bus reset is received, or suspend is detected (1) Peripheral C ontroller Function: e xa mple of SOFR interrupt generated after SOF Lock SOF falling SOF Packet SOF SOF falling Number 6 7 3 0 1 2 3 4 5 6 7 0 4 1 2 3 4 5 6 7 0 1 6 Frame Number (FRNM bit) SOFR Interrupt SOF interpolation generated interpolation generated SOF Interrupt output by SOF interpolation function (2) Peripheral C ontroller Function: e xa mple of SOFR interrupt generated before S OF Lock SOF falling SOF SOF SOF falling SOF falling Packet Number 7 0 1 SOF 6 7 0 7 not 0 1 7 0 4 1 2 7 0 1 6 Frame Number (FRNM bit) 0 (value befo re S OF lock) interpolation not generated SOF interpolation SOF interpolation generated generated SOF Lock No interrupt output due to no lock No interrupt output due to no lock Interrupt output by SOF interpolation function SOFR Interrupt Figure 3.12 SOFR Interrupt Output Timing Example Rev1.01 Oct 17, 2008 page 125 of 183 R8A66597FP/DFP/BG 3.3 Pipe Control Table 3.10 provides a list of pipe settings for the controller. In USB data transfers, data transmission is executed in logic pipes called endpoints. The R8A66597 controller comes with nine pipes for data transfer. Each pipe can be set to meet the requirements of the user system. Table 3.10 Pipe Settings Register Name PIPESEL Bit Name Setting Description Specifies the pipe number for setting the PIPEBU, PIPEMAXP, PIPEPERI registers. Comments Refer to 2.16.1 more details. DCPCFG PIPECFG TYPE BFRE DBLB CNTMD Specifies the transfer type Selects BRDY interrupt mode Selects single or double buffer Selects continuous transfer or non-continuous transfer DIR EPNUM SHTNAK Selects transfer direction (read or write) Endpoint number Disables pipe when transfer is completed. PIPEBUF BUFSIZE Buffer memory size BUFNMB Buffer memory number DCPMAXP PIPEMAXP PIPEPERI DEVSEL MXPS IFIS Selects device Maximum packet size Buffer flash Refer to 2.16.2 for more details. PIPE1-5: can be set Refer to 2.16.3, 3.4.3.4, and 3.4.3.5 for more details. PIPE1-5: can be set Refer to 2.16.4 and 3.4.1.4 for more details. PIPE1-2: can be set (in bulk transfer setting only) PIPE3-5: can be set For continuous send/receive, set the buffer size in multiples of the payload. Refer to 2.16.5 and 3.4.1.5 for more details. Set to IN or OUT Refer to 2.16.7 and 3.4.2.1 for more details. Refer to 2.16.8 for more details. DCP: can be set PIPE 1-2: can be set (in bulk transfer setting only) PIPE 3-5: can be set Refer to 2.16.6 for more details. DCP: cannot be set (fixed at 256 bytes) PIPE1-5 can be set (set in 64 byte units up to a max of 2K bytes) PIPE6-9: cannot be set (fixed at 64 bytes) Refer to 2.16.9 and 3.4.1 for more details. DCP: cannot be set (fixed at areas 0-3) PIPE1-5: can be set (between areas 8 and 135 (0x87) PIPE6-9: cannot be set (fixed at areas 4-7) Refer to 0 and 3.4.1 for more details. Refer to 2.16.11 for more details. Refer to 2.16.12 and 0 for more details. PIPE1-2: can be set (in isochronous transfer setting only) PIPE3-9: cannot be set Refer to 2.16.13 and 3.9.5 for more details. PIPE1-2: can be set (in isochronous transfer setting only) PIPE3-9: can be set (only when Host Controller function is selected) Refer to 2.16.14 and 3.9.3 for more details. Refer to 2.17.1 and 3.4.1.1 for more details. Refer to 2.17.2 and 3.4.1.1 for more details. Only DCP can be set Can only be controlled when Host function is selected Only DCP can be set Can only be controlled when Host function is selected Can only be controlled when Host function is selected Can only be controlled when Host function is selected IITV Interval counter DCPCTR PIPExCTR BSTS INBUFM SUREQ SUREQCLR CSCLR CSSTS Buffer Status IN buffer monitor SETUP request SUREQ clear CSSTS clear Split Transaction Status Confirm page 126 of 183 Rev1.01 Oct 17, 2008 R8A66597FP/DFP/BG Register Name Bit Name ATREPM ACLRM Setting Description Auto response mode Auto buffer clear Comments PIPE1-5: can be set Can only be controlled when Peripheral function is selected Can be enabled and disabled when buffer memory is read-enabled Refer to 2.17.6 and 2.17.15 for more details. Clear data toggle bit Refer to 2.17.7 and 3.3.4 for more details.. Set data toggle bit Refer to 2.17.8 and 3.3.4 for more details. Confirm data toggle bit Refer to 2.17.9 and 3.3.4 for more details. Refer to 2.17.10 for more details. Refer to 2.17.11 and 3.3.2 for more details.. PIPE1-5: can be set Refer to 2.18.2 for more details. PIPE1-5: can be set Refer to2.18.3 for more details. PIPE1-5: can be set Refer to 2.18.1 for more details. Can be set only when Host function is selected Refer to 2.19.1 for more details. Can be set only when Host function is selected Refer to 2.19.2 for more details. Can be set only when Host function is selected Refer to 2.19.3 for more details. Can be set only when Host function is selected Refer to 2.19.4 for more details. SQCLR SQSET SQMON PBUSY PID TRENB TRCLR PIPExTRN DEVADDx TRNCNT UPPHUB Sequence toggle bit clear Sequence toggle bit set Sequence toggle bit confirm Confirm pipe busy Response PID Transaction count enable Current transaction counter clear Transaction counter Transmission targeted device connected HUB register connected Transmission targeted device connected HUB port Transfer speed of the transmission targeted device Root hub port number for the transmission targeted tree PIPExTRE HUBPORT USBSPD RTPORT Rev1.01 Oct 17, 2008 page 127 of 183 R8A66597FP/DFP/BG 3.3.1 Maximum Packet Size Setting Maximum packet size for each pipe is set in the MXPS bit of the DCPMAXP and PIPEMAXP registers. DCP and pipes 1-5 can be set with any maximum packet size defined in the USB specifications. Pipes 6-9 are limited to maximum packet size of 64 bytes. Set the maximum packet size before starting transfers (set "PID=BUF"). DCP: set to "64" for Hi-Speed operation DCP: set to "8", "16", "32", or "64" for Full-Speed operation PIPE 1-5: set to "512" for Hi-Speed bulk transfer PIPE 1-5: set to "8", "16", "32", or "64" for Full-Speed bulk transfer PIPE 1-2: set a value from "1" to "1024" for Hi-Speed isochronous transfer PIPE: 1-2: set a value from "1" to "1023" for Full-Speed isochronous transfer. For more details, see section 3.9. PIPE 6-9: Set a value from "1" to "64". High-bandwidth transfers are not yet supported in interrupt and isochronous transfers. Rev1.01 Oct 17, 2008 page 128 of 183 R8A66597FP/DFP/BG 3.3.2 Response PID Set the response PID for each pipe with the PID bit of the DCPCTR and PIPExCTR registers. (1) Response PID setting for Host Controller function The response PID specifies the transaction execution. (a) NAK setting: Pipe is in disabled status; transaction cannot be executed. (b) BUF setting: transaction is executed according to the buffer memory status. For OUT direction, when there is send data in the buffer memory, an OUT token is issued. For IN direction, if there is empty space in the buffer memory and it is receive enabled, an IN token is issued. (c) STALL setting: Pipe is in the disabled status; transaction cannot be executed. Use the SUREQ bit to perform the DCP setup transaction. (2) Response PID setting for Peripheral Controller function The response PID specifies the response to a transaction from the Host. (a) NAK setting: Always sends a NAK response when a transaction is issued. (b) BUF setting: Responds to the transaction in accordance with the buffer memory status. (c) STALL setting: Always sends a STALL response when a transaction is issued. Regardless of the value set in the PID bit, an ACK is always sent as a response to a setup transaction and the USB request is stored in corresponding registers. Based on the results of the transaction, the controller may trigger the PID bit to be written. The controller will trigger a write event to the PID bit in the following cases. (1) H/W setting of Response PID when Host Controller function is selected (a) NAK setting: In the following conditions, the PID bit is set to NAK and token issuance is automatically stopped. (i) In transfer types other than isochronous, when a receive error, such as No Response, bit stuffing error or CRC error, occurs 3 times consecutively in response to a transferred token (ii) In an isochronous transfer, when a receive error, such as bit stuffing error or CRC error, occurs 3 times consecutively in response to a transferred token (iii) When DCPCFG register SHTNAK bit is set to "1" and a short packet is received in the data stage of a control read transfer (iv) When a short packet is received during a bulk transfer and PIPECFG register SHTNAK bit is set to "1" (v) When a transaction counter is completed during a bulk transfer and PIPECFG register SHTNAK bit is set to "1" (b) BUF setting: the BUF cannot be written by the controller (c) STALL setting: In the following conditions, the PID bit is set to STALL and token issuance is automatically stopped. (i) STALL is received in response to a sent token (ii) Received packet exceeds maximum packet size (2) H/W setting of Response PID when Peripheral Controller function is selected (a) NAK Setting: (i) When SETUP token is received normally (only DCP) (ii) In bulk transfers when PIPECFG register SHTNAK bit is set to "1" and short packet is received (iii) In bulk transfers when SHTNAK bit is set to "1" and the transfaction counter is completed. (b) BUF setting: the BUF cannot be written by the controller (c) STALL setting: (i) When a maximum packet size over error is detected for a received data packet (ii) When a control transfer sequence error is detected Rev1.01 Oct 17, 2008 page 129 of 183 R8A66597FP/DFP/BG 3.3.3 PIPE Information Modification Process The following pipe control register bits can be re-written only when USB transmission is disabled ("PID=NAK"). Figure 3.13 shows the process for switching the pipe control register from the USB transmission enabled status. Registers that are prohibited setting when the USB transmission is enabled ("PID=BUF"): (1) All bits of DCPCFG and DCPMAXP registers (2) DCPCTR register SQCLR, SQSET, and CSCLR bits (3) All bits of PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI registers (4) PIPExCTR register ATREPM, ACLRM, SQCLR, and SQSET bits (5) All bits of PIPExTRE and PIPExTRN registers (6) All bits of DEVADDx register In addition to the settings described for the CSCLR bit and all bits of the DEVADDx register, setup methods described in Chapter 2 for each bit must also be complied with. Request pipe information modification Set "NAK" in PID of corresponding pipe Wait until CSSTS bit of corresponding pipe goes to "0" for Host function only Wait until PBUSY bit of corresponding pipe goes to "0" Start pipe information modification Figure 3.13 PIPE Information Modification Process from USB Transmission Enabled (PID=BUF") Status In addition, the following pipe control register bits can only be re-written with pipe information that is not set in the CURPIPE bit of CPU/DMA0/DMA1-FIFO ports. Register cannot be set while corresponding pipe number is set in FIFO port CURPIPE bits: (1) All bits of DCPCFG and DCPMAXP registers (2) All bits of PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI registers When modifying information of a pipe, specify other pipe number in the CURPIPE bit. Also, after setting the DCP pipe information, execute the clear process for the buffer using the BCLR bit. 3.3.4 Data PID Sequence Bit When a normal data transfer occurs in the control transfer data stage, bulk transfer or interrupt transfer, the controller automatically toggles the data PID sequence bit. The next data PID sequence bit for data transfer can be confirmed in the SQMON bit in the DCPCTR or PIPExCTR registers. The sequence bit is switched in the ACK handshake receive timing when data is sent or in the ACK handshake send timing when data is received. The data PID sequence bit can also be modified for the SQCLR and SQSET bits of the DCPCTR and PIPExCTR registers. Rev1.01 Oct 17, 2008 page 130 of 183 R8A66597FP/DFP/BG For control transfers when the Peripheral Controller function is selected, the controller automatically sets the sequence bit for stage transitions. In control transfers when the Peripheral Controller function is selected, the controller automatically sets the sequence bit when the stage transitions. The bit goes to DATA0 when the setup stage completes, and responds with DATA1 in the status stage. Therefore, the bit does not need to be set with software. In control transfers when the Host Controller function is selected, the sequence bit must be set with software when the stage transitions. Note that regardless of whether the Host or Peripheral function is selected, the data PID sequence bit must be set with software when a ClearFeature request is sent or received. Finally, the sequence bit cannot be controlled through the SQSET bit for the isochronous transfer setup pipe. Rev1.01 Oct 17, 2008 page 131 of 183 R8A66597FP/DFP/BG 3.4 Buffer Memory This section describes operations concerning the controller's built-in buffer memory. Unless specified, the operations apply to both Host and Peripheral function selections. 3.4.1 Buffer Memory Allocation Figure 3.14 provides an example buffer memory map of the controller. The buffer memory is an area shared by the CPU that controls the user system and this controller. The various buffer memory conditions determine access authority for the user system (CPU side) and/or this controller (SIE side). The buffer memory is set into independent areas for each pipe. The memory area is set in 64-byte blocks by the block start addresses and the number of blocks (set in PIPEBUF register BUFNMB bit and BUFSIZE bit). When selecting the continuous transfer mode with the PIPExCFG register CNTMD bit, make sure the BUFSIZE bit is set in integral multiples of the maximum packet size. Also, when selecting the double buffer in the PIPExCFG register DBLB bit, 2 areas of the memory specified in the PIPEBUF register BUFSIZE bit will be allocated for the corresponding pipe. Three FIFO ports are used for access (data read/write) to the buffer memory. The pipe number of the pipe assigned to each FIFO port is specified in the C/DxFIFOSEL register CURPIPE bit. The buffer status (enable/disable access for data read/write to buffer memory from CPU) of each pipe can be confirmed in the BSTS and INBUFM bits of the DCPCTR and the PIPExCTR registers. Also, FIFO port access authorization can be confirmed in the C/DxFIFOCTR register FRDY bit. Rev1.01 Oct 17, 2008 page 132 of 183 R8A66597FP/DFP/BG FIFO Port No. Buffer memory PIPE assignment exam ple PIPE0 (DCP) BUFNMB (BUFSIZE+1) x (DBLB+1) PIPE6 PIPE7 PIPE8 PIPE9 PIPE5 PIPEBUF reg set value PIPECFG reg DBLB bit set value CFIFO Port CURPIPE=6 0 1 2 3 4 5 6 7 8 9 14 15 16 22 23 24 31 32 47 48 63 64 79 80 95 96 137 No setup register (BUFNMB=0, BUFSIZE=3, DBLB=0) fixed equivalently) BUFNMB=4, BUFSIZE=0 BUFNMB=5, BUFSIZE=0 BUFNMB=6, BUFSIZE=0 BUFNMB=7, BUFSIZE=0 BUFNMB=8, BUFSIZE=7 DBLB=0 DBLB=0 DBLB=0 DBLB=0 DBLB=0 D0FIFO Port CURPIPE=1 D1FIFO Port CURPIPE=3 PIPE1 BUFNMB=16, BUFSIZE=7 DBLB=1 PIPE2 BUFNMB=32, BUFSIZE=15 DBLB=0 PIPE3 BUFNMB=48, BUFSIZE=15 DBLB=1 PIPE4 BUFNMB=80, BUFSIZE=15 DBLB=0 unassigned Fixed area (cannot be changed by software) Setting examples (can be changed by software) Figure 3.14 Buffer Memory Map Example Rev1.01 Oct 17, 2008 page 133 of 183 R8A66597FP/DFP/BG 3.4.1.1 Buffer Status Table 3.11 shows the buffer statuses for the controller. The buffer memory status can be confirmed with the BSTS and INBUFM bits. The direction of buffer memory access can be specified in the PIPExCFG register DIR bit or the CFIFOSEL register ISEL bit (in the DCP setting). The INBUFM bit is only valid in the send direction of pipes 1 to 5. When the send-side transfer pipe is set to double buffer, the BSTS bit is used to determine the status of the CPU-side buffer and the INBUFM bit is used to determine the status of the SIE-side buffer. If the write event to the FIFO port using the CPU (DMCA) is slow and the buffer empty space cannot be determined by the BEMP interrupt, send completion can be confirmed with the INBUFM bit. Table 3.11 Buffer Status Confirmation with BSTS Bit ISEL or DIR 0 (receive direction) 0 (receive direction) BSTS 0 1 Buffer Memory Status No receive data or now receiving. FIFO port is read-disabled. Receive data is in FIFO buffer or zero-length packet is received. FIFO port is read-enabled. However, when zero-length packet is received the FIFO port is read-disabled and the buffer must be cleared. Send is not completed. FIFO port is write-disabled. Send is completed. FIFO port is write-enabled. 1 (send direction) 1 (send direction) 0 1 Table 3.12 Figure 3.12 Buffer Status Confirmation with INBUFM Bit DIR 0 (receive direction) 1 (send direction) 1 (send direction) INBUFM Invalid 0 1 Buffer Memory Status Invalid Send data transfer is complete. No send data in FIFO buffer Send data is written from FIFO port. Send data is in FIFO buffer. 3.4.1.2 Buffer Clear Table 3.13shows the buffer memory clear conditions for the controller. The following 4 bits can clear the buffer memory. Table 3.13 Buffer Clear Bits Bit Name Register Function BCLR CFIFOCTR register DxFIFOCTR register Clears the CPU-side buffer memory of the pipe assigned to the CFIFO port or DxFIFO port SCLR CFIFOSIE register Clears the SIE-side buffer memory of the pipe assigned to the CFIFO port. DCLRM DxFIFOSEL register automatically clears the buffer memory after data is read from the specified pipe. Convenient function when using DMAC to read data. Refer to 3.4.3.4 Set "DCLRM=1" to enable mode. Set "DCLRM=0" to disable mode. ACLRM PIPExCTR register Clears the SIE-side buffer memory of the corresponding pipe by writing "1" and "0" consecutively to the ACLRM bit. Set "ACLRM=1" to enable mode. Set "ACLRM=0" to disable mode. Setup Method Clear the buffer memory by setting "BCLR=1". (Automatically returns to "BCLR=0") Clear the buffer memory by setting "SCLR=1". (Automatically returns to "SCLR=0") Rev1.01 Oct 17, 2008 page 134 of 183 R8A66597FP/DFP/BG 3.4.1.3 Buffer Area Table 3.14shows the buffer memory map for the controller. The buffer memory consists of a fixed area in which pipes are pre-assigned and a user area in which the user can set blocks as needed. The DCP buffer is a fixed area used only for control read transfers and control write transfers. Pipes 6-9 are pre-assigned to areas. When not using one of these pipes, the user can assign one of pipes 1-5 to the unused pipe area and utilize as a user area. Be careful to set the pipe areas so that they do not overlap. In addition, set the buffer size so that it is larger or equal than the maximum packet size. Table 3.14 Buffer Memory Map Buffer Memory Number 0-3 4 5 6 7 8 - 135 (0x87) Buffer Size 256 bytes (64 bytes x 4 blocks) 64 bytes 64 bytes 64 bytes 64 bytes 8192 bytes (64 bytes x 128 blocks) Assignable PIPE DCP-only fixed area PIPE 6 fixed area PIPE 7 fixed area PIPE 8 fixed area PIPE 9 fixed area PIPE 1-5 3.4.1.4 Buffer Memory Specifications (Single/Double Setting) Pipes 1-5 can be specified as single or double buffers with the PIPExCFG register DBLB bit. The double buffer is a function that assigns doulbe areas in the specified memory with the PIPEBUF register BUFSIZE bit for one pipe. Figure 3.14 is a double buffer setting example of PIPE1 and PIPE3 as seen in the buffer memory map example. Rev1.01 Oct 17, 2008 page 135 of 183 R8A66597FP/DFP/BG 3.4.1.5 Buffer Memory Operations (continuous transfer setting) The CNTMD bit in either the DCPCFG or PIPExCFG register can be used to select the continuous or non-continuous transfer mode. Selection can be made for pipes 0-5. The continuous transfer mode sends/receives multiple transactions continuously. When the continuous transfer mode is selected, data can be transferred up to the buffer size assigned to each pipe, without interrupts to the CPU. In the continuous send mode, the write data is sent divided into maximum packet sizes. If the send data that is less than the buffer size (short packets or packets in integral multiples of the maximum packet size that are smaller than the buffer size), "BVAL=1" must be set after the send data is written. In the continuous receive mode, the BRDY interrupt is not generated until packets are received up to the buffer size, the transaction count is completed, or a short packet is received. Figure 3.15shows a status transition example of the controller's CNTMD bit and buffer memory. (1) CNTMD=0, Packet receive example (DBLB=0) Buffer Memory 1 packet of receive data Unused area (2) CNTMD=1, Packet receive example (DBLB=0) Buffer Memory 1 packet of receive data (Maximum Packet Size) Transition to read-enabled status 1 packet of receive data (Maximum Packet Size) 1 packet of receive data (Maximum Packet Size) 1 packet of receive data Transition to read-enabled status (3) CNTMD=0, Packet send example (DBLB=0)) Buffer Memory 1 packet of send data Unused area Transition to send-enabled status (4) CNTMD=1, Packet send example (DBLB=0) Buffer Memory 1 packet of send data (Maximum Packet Size) 1 packet of send data (Maximum Packet Size) 1 packet of send data (Maximum Packet Size) 1 packet of send data (Maximum Packet Size) Transition to send-enabled status Figure 3.15 CNTMD Bit and Buffer Memory Status Transition Example Rev1.01 Oct 17, 2008 page 136 of 183 R8A66597FP/DFP/BG 3.4.2 FIFO Port Function This section describes the FIFO port functions. Table 3.15 shows definitions of the FIFO port function settings for the controller. When data write access is enabled and data is written up to buffer full state (in non-continuous transfer: maximum packet size), the port automatically goes to the USB bus send enabled status. To enable data send of less than buffer full (in non-continuous transfer: less than number of maximum packet size), the port must be set to write complete in the C/DxFIFOCTR register BVAL bit (DMA transfer: DEND signal). To send a zero-length packet, the port must be set to write complete in the BVAL bit in addition to clearing the buffer with the BCLR bit of the same register. When a read access is executed, if all the data is read, the port automatically goes to the new packet receive enable status. However, when a zero-length packet is received (DTLN=0), the data cannot be read and the buffer must be cleared in the BCLR bit of the same register. The receive data length is confirmed in the C/DxFIFOCTR register DTLN bit. Table 3.15 FIFO Port Function Settings Register Bit C/DxFIFOSEL Bit Name RCNT REW DCLRM Function Selects DTLN read mode Buffer memory window (re-read, re-write) Automatically clears buffer memory after specified pipe received date is read DREQ signal assert FIFO port access bit width FIFO port endian control FIFO port access direction Selects Current PIPE Buffer memory write end Clears CPU-side buffer memory Monitors FIFO port ready Confirms received data length Buffer memory write end Refernece 2.8.4 3.4.2.2 2.8.11 3.4.1.2 3.4.3.4 3.4.3 2.8.5 3.4.2.1 2.8.6 2.8.7 3.4.2.1 2.8.8 2.8.16 2.8.17 3.4.1.2 2.8.18 2.8.19 0 3.4.3.3 Notes DxFIFO only DREQE MBW BIGEND ISEL CURPIPE BVAL BCLR FRDY DTLN DEND DxFIFO only DCP only C/DxFIFOCTR External pin DMA transfer only 3.4.2.1 FIFO Port Selection Table 3.16 shows the list of pipes that can be selected in each FIFO port. The pipes to be accessed are selected with the C/DxFIFOSEL register CURPIPE bit. After selecting the pipes, confirm that the CURPIPE value written was read correctly (if the previous pipe number is read out, this indicates the controller is still processing the pipe change), then confirm that "FRDY=1" and access the FIFO port. Also, select the bus width for the FIFO port access with the MBW bit. The buffer memory access direction is determined by the ISEL bit for DCP, and the PIPExCFG register DIR bit for all other pipes. Table 3.16 FIFO Port Access by PIPE PIPE DCP PIPE 1-7 Access Method CPU access CPU access DMA access Usable Ports CFIFO port register CFIFO port register DxFIFO port register DxFIFO port register 3.4.2.2 REW Bit The REW bit the C/DxFIFOSEL register in allows the user to temporarily stop the current pipe access, execute access of another pipe, then continue the current pipe access process again. Rev1.01 Oct 17, 2008 page 137 of 183 R8A66597FP/DFP/BG 3.4.2.3 Transaction Counter (read direction) The transaction counter enables the controller to recognize transfer completion after the specified number of transactions has completed in the data packet receive direction. The transaction counter is a function that operates in correspondence to pipes set in the receive direction. This function can be used for read events from any FIFO port. The transaction counter includes the TRNCNT register, which specifies the number of transactions, and the current counter that counts the number of internal transactions. When the current counter reaches the specified number of transactions, the buffer memory goes to the read-enabled status, even if it is not full. When the Host Controller function is selected, not only is the buffer memory read-enabled, but tokens cannot be issued by the controller to the corresponding pipe. The TRCLR bit can be used to initialize the current counter in the transaction counter function so that the transaction can counted from the beginning again. Also, the information read from the TRNCNT register can be switched by setting the TRENB bit accordingly. TRENB=0: the set transaction counter value is read out TRENB=1: the current counter value counted internally is read out Modification conditions for the CURPIPE are as follows: (1) Do not change the CURPIPE setting until the transaction in the specified pipe is completed. (2) The CURPIPE cannot be changed unless the current counter is cleared. TRCLR bit usage conditions are as follows. (1) The current counter cannot be cleared while a transaction is in process and "PID=BUF". (2) The current counter cannot be cleared when data remains in the buffer. Rev1.01 Oct 17, 2008 page 138 of 183 R8A66597FP/DFP/BG 3.4.3 DMA Transfer (DxFIFO Port) 3.4.3.1 DMA Transfer Outline Pipes 1-9 can be used for FIFO port access with DMAC. When access becomes enabled for the pipe set by DMA, the DREQ signal is asserted. The DMA transfer can be executed in the cycle steal transfer mode, which asserts the DREQ signal every time one data (8-bit or 16-bit) is transferred, or in the burst transfer mode, in which the DREQ signal is continually asserted until all data transfers in the buffer memory are completed. The timing is described in detail in "Chapter 4. Electric Characteristics." Select the FIFO port transfer unit (8 bits or 16 bits) with the DxFIFOSEL register MBW bit and the DMA transfer pipe with the CURPIPE bit. Note that the pipe (value set in CURPIPE bit) should not be changed during a DMA transfer. 3.4.3.2 DMA Control Signal Selection Select the pin for DMA transfers in the DMAxCFG register DFORM bit and control the DREQx_N pin with the DxFIFOSEL register DREQE bit. Table 3.17provides the list of DMA control pins and Figure 3.16 shows the FIFO port access method and the DMA control pin. Table 3.17 DMA Control Pin List Register Access Method CPU bus 0 CPU bus 1 CPU bus 2 CPU bus 3 SPLIT bus *1) DREQE 0 1 1 1 1 DFORM 0 0 1 1 1 DATA Bus CPU CPU CPU CPU SPLIT DREQ Pin DACK RD/WR ADDR +CS *1) *1) Reference 0 0 0 0 1 0 0 0 1 0 CPU access DMA through CPU bus DMA through CPU bus DMA through CPU bus SPLIT bus When setting this access method, set the CS_N to inactive (fix to "High") while accessing the DxFIFO port. CPU bus 1 DMA transfer DREQ DACK RD/W R CS ADDR D15-0 DEND CPU bus 2 DMA transfer SPLIT bus DMA transfer DREQ DACK SD7-0 DEND Figure 3.16 FIFO Port Access and DMA Control Pin Rev1.01 Oct 17, 2008 page 139 of 183 R8A66597FP/DFP/BG 3.4.3.3 DEND Pint The controller can end a DMA transfer using the DEND pin. The DEND pin also functions as input/output according to the USB data transfer direction. (1) Buffer memory read direction The DEND pin can perform as an output pin and notify the external DMA controller of the last data transfer. The DEND signal assert conditions can be set in the DMAxCFG register PKTM bit. Table 3.18 provides a list of DEND pin asserts. Table 3.18 DEND Pin Assert List BRDY Receive short Receive Receive zero-length generated due packet other than Zero-Length packet when buffer PKTM to packet zero-length packet when buffer is EMPTY *2) receive is not EMPTY 0 Assert No assert Assert Assert Assert 1 Assert Assert Assert Assert No assert *1) The DREQ signal is not asserted if a zero-length packet is received when the buffer is empty. (2) Buffer memory write direction The DEND pin becomes an input pin and the buffer memory goes to send-enabled (same status as when "BVAL=1") when an active edge is detected. Event Transaction Count End 3.4.3.4 DxFIFO Automatic Clear Mode (DxFIFO port read direction) When a data read event of the controller buffer memory is completed with setting DxFIFOSEL register DCLRM bit to "1", the buffer memory of the corresponding pipe is automatically cleared. Table 3.19 shows the correspondence between the packet received and the buffer memory clear process by software in each setting. As indicated in Table 3.19, the buffer clear conditions differ according to the BFRE bit set value, even for statuses in which clear is normally required, using the DCLRM bit eliminates the need for buffer clear by software, enabling DMA transfers without the use of software. Note that this function only has supports the buffer memory read direction setting. Table 3.19 Correspondence of Packet Receive and Buffer Memory Clear Process by Software Register Setting Buffer state when packet received DCLRM = 0 BFRE=0 BFRE=1 Clear unnecessary Clear necessary Clear unnecessary Clear unnecessary Clear unnecessary Clear necessary Clear necessary Clear necessary DCLRM=1 BFRE=0 BFRE=1 Clear unnecessary Clear unnecessary Clear unnecessary Clear unnecessary Clear unnecessary Clear unnecessary Clear unnecessary Clear unnecessary Buffer full Zero-Length packet received Normal short packet received Transaction count end Rev1.01 Oct 17, 2008 page 140 of 183 R8A66597FP/DFP/BG 3.4.3.5 BRDY Interrupt Timing Selection Function The PIPECFG register BFRE bit can be set so that the BRDY interrupt is not generated when a data packet of maximum packet size is received. When using a DMA transfer, this function enables an interrupt to be generated only when the last data is received. The last data indicates either a short packet receive or the transaction count end. By setting "BFRE=1", the BRDY interrupt will be generated after the received data is read. By reading the DnFIFOCTR register DTLN bit, the receive data length of last data packet received just before the BRDY interrupt was generated can be confirmed. Table 3.20 shows the timing of the BRDY interrupt. Table 3.20 BRDY Interrupt Generation Timing List BFRE = "1" No interrupt generated When packet is received When read event of data received Normal short packet received When packet is received from buffer memory is completed When read event of data received Transaction count end When packet is received from buffer memory is completed The BFRE bit function is only valid in the read direction of the buffer memory. When in the write direction, fix the BFRE bit to "0". Buffer state when packet received Registration Setting Buffer full (normal packet received) Zero-Length packet received BFRE = "0" When packet is received When packet is received Rev1.01 Oct 17, 2008 page 141 of 183 R8A66597FP/DFP/BG 3.4.4 FIFO Port Access Enable Timing This section describes the FIFO port access enable timing. 3.4.4.1 FIFO Port Access Enable Timing at Pipe Switch Figure 3.17 shows the timing diagram up to confirmation of the FRDY and DRLN bits when the pipe specified by the FIFO port is switched (modified C/DxFIFOSEL register CURPIPE bit). When the CURPIPE bit is modified, first confirm that the written CURPIPE value was read correctly (if the previous pipe number is read out, this indicates the controller is still processing the pipe modification), then confirm that "FRDY=1" and access the FIFO port. The same timing applies to modification of the ISEL bit for the CFIFO port. Write to CURPIPE bit WR N CURPIPE FRDY DTLN PIPE-A PIPE-A PIPE-A Undetermined Undetermined PIPE-B PIPE-B PIPE-B max 450ns max 100ns min 20ns Figure 3.17 FRDY, DRLN Fix Timing after Pipe Switch 3.4.4.2 FIFO Port Access Enable Timing after Double Buffer Read/Write is Completed Figure 3.18 shows the timing diagram up to when access is enabled for the second buffer, after the buffer read or write is completed in the double buffer mode. In the double buffer mode, always access the FIFO port after waiting 300ns after the access just before the toggle. The same timing is applied to sending a short packet by setting "BVAL=1" in the IN direction pipe. Access just before buffer toggle WR_N / RD_N CURPIPE FRDY DTLN Buffer-A Buffer-A Undetermined max 300ns min 20ns PIPE-A Buffer-B Buffer-B Figure 3.18 Figure 3.18 FRDY, DTLN Confirmation Timing after Double Buffer Read/Write Complete Rev1.01 Oct 17, 2008 page 142 of 183 R8A66597FP/DFP/BG 3.5 Data Setup Timing This section describes the OBUS bit that sets the split bus timing. The same operations apply in both Host and Peripheral Function selections. The timing of the SD0-7 and DEND pins can be modified through the DMAxCFG register OBUS bit as described in Table 3.21. The OBUS bit function is only valid for DMA transfers using a split bus. When using the CPU bus for DMA transfers, the OBUS bit setting is ignored. Table 3.21 Operation Differences According to OBUS Bit Setup Value Direction Read OBUS Bit Setting 0 Operation SD0-7/DEND signals are output normally, regardless of the control signal *1. If the control signal is negated, the next data is output. Therefore, the DMAC data setup timing is secured and Hi-Speed DMA transfer is enabled. 1 SD0-7/DEND signals are output after the control signal is asserted. SD0-7/DEND signals go to Hi-z if the control signal is negated. Write 0 SD0-7/DEND signals are output normally, regardless of the DACKx_N signal. The DMAC can output the next data before the DACKx_N signal is asserted. Therefore, the controller data setup timing is secured and Hi-Speed DMA transfer is enabled. 1 SD0-7/DEND signals are input-enabled only when the DACKx_N signal is asserted. SD0-7/DEND signals are ignored if the DACKx_N signal is negated. *1) The control signal indicates DACKx_N when DMAxCFG register DFORM [9 - 7] is "100". When "OBUS=0" is set in the read direction, SD0-7/DEND signal are always output. Note that, therefore, when sharing the bus with another device, "OBUS=1" shall be set. When "OBUS=0" is set in the write direction, SD0-7/DEND signals are always input-enabled. Do not allow the signals to be used as mid-rail voltage. Figure 3.19 shows the configuration of data setup timing by the OBUS bit. OBUS=1: normal mode DREQ DACK SD7-0 DEND OBUS=0: High-Speed mode Figure 3.19 Data Setup Timing Configuration Rev1.01 Oct 17, 2008 page 143 of 183 R8A66597FP/DFP/BG 3.6 Control Transfer (DCP) Data transfer in the data stage of the control transfer uses the default control pipe (DCP). The DCP buffer memory is a 256-byte single buffer fixed area used for both control read and control write events. Only the CFIFO port is enabled for access to the buffer memory. 3.6.1 Control Transfer with Host Controller Function Stage transition is managed for control transfers by software in the following manner. When the Peripheral Device corresponding to the control transfer is in Low-Speed operation, set the SOFCFG register TRNENSEL bit to "1" for the control transfer period with the device. 3.6.1.1 Setup Stage The following registers are used for USB request send events in the setup transaction: USBREQ, USBVAL, USBINDX, and USBLENG. By writing a setup packet data to the registers and setting "1" in the DCPCTR register SUREQ bit "1", the set data will be sent as the setup transaction. The SUREQ bit is written to "0" by H/W after the transaction is completed. Do not use the above-listed USB request registers while "SUREQ=1". After Peripheral Device attachment is detected, issue the initial setup transaction for the device by setting the DCPMAXP register DEVSEL bit to "0" and setting the DEVADD0 register UPPHUB, HUBPORT, USBSPD, and RTPORT bits as described in the sequence above. After the Peripheral device has transitioned to the Address state, issue the setup transaction in the above-described sequence after setting the assigned USB Address value to the DEVSEL bit and setting each bit of the DEVADDx register that corresponds to the USB Address. For example when "DEVSEL=0x2", set the DEVADD2 register; when "DEVSEL=0xA", set the DEVADDA register. After the transaction is sent, an interrupt request is issued in response from the peripheral (INTSTS1 register SIGN bit and SACK bit). The setup transaction result can be confirmed by this interrupt request. The setup transaction data packet is always the DATA0 data packet (USB request), regardless of the contents of the DCPCTR register SQMON bit. 3.6.1.2 Data Stage The data stage uses the DCP buffer memory for data transfers. To access the DCP buffer memory, set the access direction in the CFIFOSEL register ISEL bit. Also set the transfer direction in the DCPCFG register DIR bit. The first packet in the data stage must transmit the data PID as DATA1. Execute the transaction by setting the data PID as DATA1 in the DCPCFG register SQSET bit and setting the PID bit to BUF. Data transfer completion is detected by the BRDY or BEMP interrupts. In control write transfers, when the send data is in integral multiples of the maximum packet size, use software to output a zero-length packet as the last packet. For transmissions in the data send direction in Hi-Speed operations, the user can select PING or OUT for the first token to be issued by setting the DCPCTR register PINGE bit. PING packet control is the same as that for bulk transfers. Refer to 3.7.1 for more details. 3.6.1.3 Status Stage The status stage transfers data in a zero-length packet in the opposite direction of the data stage. As in the data stage, the DCP buffer memory is used for data transfers. Transactions are executed in the same procedure as that of the data stage. The status stage data packet must transmit the data PID as DATA1. Make sure data PID is set as DATA1 in the DCPCFG register SQSET bit. Also, for zero-length packet receive events, confirm the received data length in the CFIFOCTR register DTLN bit after the BRDY interrupt is generated, then clear the buffer memory with the BCLR bit. For transmissions in the data send direction in Hi-Speed operation, the user can select PING or OUT for the first token to be issued by setting the DCPCTR register PINGE bit. Rev1.01 Oct 17, 2008 page 144 of 183 R8A66597FP/DFP/BG 3.6.1.4 PING Packet Control in Data Stage and Status Stage OUT direction PING packets are automatically sent out by the controller. When "PINGE=0" is set, the controller starts the send direction transmission with the OUT packet. If a NAK or NYET is received in response to an OUT transaction, a PING is sent. When an ACK handshake is received in response to the PING, the OUT packet is sent. < Rev1.01 Oct 17, 2008 page 145 of 183 R8A66597FP/DFP/BG 3.6.2 Control Transfer with Peripheral Controller Function Selected 3.6.2.1 Setup Stage The controller always responds with an ACK when it receives a normal setup packet. The controller operations in the setup stage are as follows. (1) When a new setup packet is received, the controller sets the following bits. (a) Sets INTSTS0 register VALID bit to "1". (b) Sets DCPCTR register PID bit to "NAK". (c) Sets DCPCTR register CCPL bit to "0". (2) When a data packet is received following the setup packet, the USB request parameters are stored in the following registers: USBREQ, USBVAL, USBINDX and USBLENG. Always set "VALID=0" in the response process to a control transfer. In the "VALID=1" state, "PID=BUF" will not be set and the data stage cannot be completed. The VALID bit function allows the controller to temporarily stop a request in-process when it receives a new USB request during a control transfer, and respond to the newest request. In addition, the controller automatically judges the direction bit (bmRequestType bit 8) and the request data length (wLength) of the received USB request and determines whether it is a control read transfer, control write transfer or no-data control transfer, and then handles the stage transition. If the sequence is incorrect, a sequence error for the control transfer stage transition interrupt occurs and is notified to the software. For more information concerning the controller stage management, refer to Figure 3.11. 3.6.2.2 Data Stage Use the DCP for data transfers in response to receiving a USB request. Before accessing the DCP buffer memory, set the access direction in the CFIFOSEL register ISEL bit. Also set the transfer direction in the DCPCFG register DIR bit. The first data packet in the data stage must transmit the data PID as DATA1. To execute the transaction, set the data PID as DATA1 in the DCPCFG register SQSET bit and set the PID bit to BUF. Data transfer completion is detected by the BRDY and BEMP interrupts. Use the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers. For control write transfers in Hi-Speed operation, a NYET handshake is sent in accordance with the buffer memory status. For more details, see Chapter 3.6.1.4, 3.6.2.3 Status Stage When the DCPCTR register PID bit status is "PID=BUF", set the CCPL bit to "1" to complete the control transfer. After the above settings, the controller automatically executes the status stage in accordance with the data transfer direction fixed in the setup stage. The detailed process is as follows. (1) Control read transfers: The controller sends a zero-length packet and receives an ACK response from the USB Host Controller. (2) Control write transfers and no-data control transfers: The controller receives a zero-length packet from the USB host and sends an ACK response. 3.6.2.4 Control Transfer Automatic Response Function The controller automatically sends a response to a normal SET ADDRESS request. If one of the following errors occurs, a response must be sent by software. (1) bmRequestType "0x00" (2) wIndex "0x00" (3) wLength "0x00" (4) wValue > "0x7F" (5) wValue 0 and DVSQ = "011" (6) wValue = 0 and DVSQ = "001" All requests other than the SET ADDRESS request must be responded to by software. Rev1.01 Oct 17, 2008 page 146 of 183 R8A66597FP/DFP/BG 3.7 Bulk Transfer (Pipes 1-5) The user can select the buffer memory usage method (single/double buffer, continuous/non-continuous transfer mode) for the bulk transfer mode. The buffer memory size can be set up to a 2K-byte double buffer. The controller manages the buffer memory state and automatically responds to PING packets and NYET handshakes. 3.7.1 PING Packet Control with Host Controller Function Selected OUT-direction PING packet are automatically sent by the controller. The controller starts the send-direction transmission with the PING packet, as shown below. When an ACK handshake is received in response to the PING, the OUT packet is sent. When a NAK or NYET is received in response to an OUT transaction, the controller returns to the PING send status. < 3.7.2 NYET Handshake Control with Peripheral Controller Function Selected Table 3.22 shows the list of responses to a token received in a bulk or control transfer. When an OUT token is received in a bulk or control transfer and there is only enough open space for one packet in the buffer memory, the controller sends a NYET response. However, when a short packet is received, the controller sends an ACK response instead of a NYET response, even under these conditions. Table 3.22 Response List for Received Tokens PID Bit Set Value NAK/STALL Buffer Memory Receive Token Status *1) SETUP IN/OUT/PING SETUP RCV-BRDY*1 OUT/PING RCV-BRDY*2 BUF OUT Response ACK NAK/STALL ACK ACK NYET Notes Receive data packet at OUT token receive Receive data packet, notify immediate receiving of next packet disabled Receive data packet, notify immediate receiving of next packet enabled Notify receive enabled Notify receive disabled Send data packet *1) RCV-BRDY*2 OUT (Short) ACK RCV-BRDY*2 PING ACK RCV-NRDY OUT / PING NAK TRN-BRDY IN DATA0 / 1 TRN-NRDY IN NAK Further response details: RCV-BRDY*1: Buffer memory has enough space for 2 packets or more when OUT/PING token is received. RCV-BRDY*2: Buffer memory has only enough space for one packet when OUT token is received RCV-NRDY: Buffer memory has not enough space for one packet when PING token is received. TRN-BRDY: Buffer memory has send data when IN token is received. TRN-NRDY: Buffer memory does not have send data when IN token is received. Rev1.01 Oct 17, 2008 page 147 of 183 R8A66597FP/DFP/BG 3.8 Interrupt Transfer (Pipes 6-9) When the Peripheral Controller function is selected, the controller executes an interrupt transfer in accordance with the period managed by the Host controller. The controller ignores (no response) PING packets in interrupt transfers. In addition, the controller does not send a NYET handshake, but responds with ACK, NAK or STALL. When the Host Controller function is selected, the token issuance timing can be set by the interval counter. Even for OUT direction transfers, the PING token in not issued but an OUT token is issued.Also, when a NYET handshake is received from the Peripheral, the interrupt transfer operates as an ACK receive. The R8A66597 controller does not support high-bandwidth transfers in the interrupt transfer mode. 3.8.1 Interval Counter for Interrupt Transfer when Host Controller Function is Selected 3.8.1.1 Operation Outline When an interrupt transfer is executed, the transaction interval is set in the PIPEPERI register IITV bit. The controller issues a token for the interrupt transfer in accordance with the set interval. 3.8.1.2 Counter Initialization The controller initializes the interval counter under the following conditions. (1) H/W reset When IITV bit is initialized (2) Buffer memory initialization by ACLRM This will initialize the counter but not the IITV bit. Set the ACLRM bit to "0" to start the count of the IITV set value again. Note that the interval counter will not be initialized in the following conditions. (1) USB bus reset and USB suspend These conditions do not initialize the IITB bit. Set the UACT bit to "1" to start the count from the value before the USB bus reset or USB suspend status. 3.8.1.3 Operations when send/receive are invalid at token issuance timing A token will not be issued in the following conditions even at normal token issuance timing. If this kind of case occurs, the transaction will be attempted again at the next interval. (1) When "NAK" or "STALL" is set in PID bit (2) When there is no empty space in the buffer memory at the timing of sending a IN-direction (receive) transfer token (3) When there is no data in the buffer memory at the timing of sending an OUT-direction (send) transfer token 3.9 Isochronous Transfer (Pipes 1-2) The controller provides the following functions for isochronous transfers. (1) Isochronous transfer error information notification (2) Interval counter (IITV bit setting) (3) Isochronous IN transfer data setup control (IDLY function) (4) Isochronous IN transfer buffer flush function (IFIS bit setting) (5) SOF pulse output function The controller does not support high-bandwidth isochronous transfers. When transmitting an isochronous pipe in a split transaction, set a value of 188 bytes or less in the MXPS bit. When the Host Controller Function is selected and isochronous transfers are being sent in two pipes at the same time, make sure the operation complies with the USB 2.0 Spec Section 5.6.3 Isochronous Transfer Packet Size Constraints. Rev1.01 Oct 17, 2008 page 148 of 183 R8A66597FP/DFP/BG 3.9.1 Isochronous Transfer Error Detection The controller manages isochronous transfer errors by software and therefore has the following error information detection functions. Table 3.23 and Table 3.24 describe the procedure in which errors are confirmed and the interrupts that are generated. (1) PID Error When the receive packet PID is corrupted (2) CRC Error and Bit Stuffing Error When an error occurs in the receive packet CRC or when the bit stuffing is corrupted. (3) Maximum Packet Size Over This indicates the data size of the receive packet is larger than the value set for the maximum packet size. (4) Overrun and Underrun (a) When Host Controller Function is selected When there is no empty space in the buffer memory at the token send timing for an IN-direction (receive) transfer When there is no data in the buffer memory at the token send timing for an OUT-direction (send) transfer. (b) When Peripheral Controller Function is selected When there is no data in the buffer memory at an IN token receive for an IN-direction (send) transfer When there is no empty space in the buffer memory at an OUT token receive for an OUT-direction (receive) transfer (5) Interval Error When Peripheral Controller Function is selected, the following will generate interval errors (a) When an IN token could not be received in the interval frame of an isochronous IN transfer (b) When an OUT token was received in other than the interval frame of an isochronous OUT transfer Table 3.23 Errors Detected at Token Receive/Send Priority of Detected Errors 1 2 Error Type PID error CRC error, bit stuffing error Generated Interrupts and Status at Time of Error Detection No interrupt generated when either Host or Peripheral Controller function is selected (ignored as corrupted packet) No interrupt generated when either Host or Peripheral Controller function is selected (ignored as corrupted packet) NRDY interrupt is generated when either Host or Peripheral Controller function is selected, and OVRN bit is set. In Host Controller function selection, token issueing is continued when the interrupt is generated. In Peripheral Controller function, a zero-length packet is sent in response to an IN token. A data packet is not received in response to an OUT token. In Peripheral Controller function selection, NRDY interrupt is generated. In Host Controller function selection, no interrupt is generated. 3 Overrun, underrun 4 Interval error Table 3.24 Errors Detected at Data Packet Receive Priority of Detected Errors 1 2 Error Type PID error CRC error, bit stuffing error Generated Interrupts and Status No interrupt generated (ignored as corrupted packet) NRDY interrupt is generated when either Host or Peripheral Controller function is selected, and CRCE bit is set. BEMP interrupt is generated when either Host or Peripheral Controller function is selected, and PID is set to "STALL". 3 Maximum packet size over error Rev1.01 Oct 17, 2008 page 149 of 183 R8A66597FP/DFP/BG 3.9.2 DATA-PID The R8A66597 controller does not support high-bandwidth transfers. When the Peripheral Controller function is selected, the following occurs in response to a received PID. (1) IN Direction (a) DATA0: sent as data packet PID (b) DATA1: not sent (c) DATA2: not sent (d) mDATA: not sent (2) OUT Direction (in Full-Speed operation) (a) DATA0: received successfully as data packet PID (b) DATA1: received successfully as data packet PID (c) DATA2: ignored packet (d) mDATA: ignored packet (3) OUT Direction (in Hi-Speed operation) (a) DATA0: received successfully as data packet PID (b) DATA1: received successfully as data packet PID (c) DATA2: received successfully as data packet PID (d) mDATA: received successfully as data packet PID 3.9.3 Interval Counter 3.9.3.1 Operation Outline The isochronous transfer interval can be set in the PIPEPERI register IITV bit. Table 3.25 shows the functions of the interval counter when the Peripheral Controller function is selected. When the Host Controller function is selected, the interval counter generates the token issuance timing and the counter operations are the same as those in interrupt transfers. Refer to 3.8.1 for more details. Table 3.25 Interval Counter Functions When Peripheral Controller Function Selected Transfer Direction IN OUT Function Send buffer flush function Token un-received notification Detection Conditions Cannot successfully receive IN token in interval frame in isochronous IN transfer Cannot successfully receive OUT token in interval frame in isochronous OUT transfer The interval count is executed for an SOF receive or a interpolated SOF. Therefore, when an SOF is damaged, the isochrony can still be maintained. Frame intervals are set as 2IITV (u) frames. 3.9.3.2 Interval Counter Initialization when Peripheral Controller function is selected The controller initializes the interval counter under the following conditions. (1) H/W reset Initializes the IITV bit. (2) Buffer memory clear by ACLRM bit This initializes the count but not the IITV bit. Set the ACLRM bit to "0" to start the count from the IITV set value. After the interval counter is initialized and a packet is successfully transferred, the interval count starts under the following conditions. (1) SOF is received after data is sent in response to an IN token in the "PID=BUF" status (2) SOF is received after data is received in response to an OUT token in the "PID=BUF" status Rev1.01 Oct 17, 2008 page 150 of 183 R8A66597FP/DFP/BG Note that the interval counter is not initialized in the following conditions. (1) When the PID is set to NAK or STALL The interval timer is not stopped at this time. The transaction will be attempted at the next interval. (2) USB bus reset or USB suspend The IITV bit is not initialized at this time. When the SOF is received, the count starts from the value before the receive. 3.9.4 Isochronous Transfer Send Data Setup when Peripheral Controller function is selected When the Peripheral Controller function is selected, after data is written to the buffer memory in the isochronous transmission, the data packet can be sent out in the next frame detected after the SOF packet. This function, called the isochronous transfer send data setup function, allows the frame that started the send to be specified. When using the buffer memory as a double buffer and both buffers have been written, only the first buffer memory to complete the write event is transfer-enabled. Therefore, even when several IN tokens are received in the same frame, only one packet of data is sent by the buffer memory. When an IN token is received, if the buffer memory is in the send-enabled state, the data transfer will be sent and a normal response returned. However, if the buffer memory is not in the send-enabled state, a zero-length packet is sent and an underrun error occurs. Figure 3.20 shows a controller send example using the isochronous transfer send data setup function when "IITV=0 (per frame)" is set. (1) Receive Start Example 1 (when send data is ready before IN token receive start) SOF Receive toke n Se nd packet SOF SOF SOF Buffer A Buffer B Empty state Writing Write end Writing Tr ansfer -enabled status Empty state Write end (2) Receive Start Example 2 (Ex. 1 of when send data is ready after IN token receive start) SOF Receive toke n Send packe t IN Zerolength Empty state Writing IN Zero length Write end Empty state IN Data-A Tran sfer- enabled status Buffer A Buffer B Empty state (3) Receive Start Example 2 (Ex. 2 of when send data is ready after IN token receive start) SOF Receive toke n Se nd packet IN Zerolength Empty state Writing SOF IN Data-A Tran sfer- enabled SOF IN Data-B Writing Tran sfer- enabled sta tus SOF Buffer A Buffer B Write e nd Writing Empty state Write end Empty state Empty state Write end (3) Example of Irregular Period IN Token receive SOF Receive toke n Se nd packet IN Zerolength Empty state Writing SOF IN Data-A Tran sfer- enabled SOF IN Zerolength Empty state Writing Tran sfer- enabled sta tus SOF IN Data-B Write end Empty state Buffer A Buffer B Write end Writing Empty state Write end Figure 3.20 Data Setup Function Operation Rev1.01 Oct 17, 2008 page 151 of 183 R8A66597FP/DFP/BG 3.9.5 Isochronous Transfer Send Buffer Flush when Peripheral Controller function is selected When the Peripheral Controller function is selected, if the controller does not receive an IN token in the interval frame in the isochronous data send but receives the () SOF packet in the next frame, the IN token is handled as a corrupted token and the buffer that is send-enabled is cleared set to the write-enabled status. At this time, if the double-buffer is used and the write event to both buffers is complete, the cleared buffer memory is assumed to be sent in the interval frame, and the other side buffer memory is set to the transfer-enabled status at the received the next (u) SOF packet. The operation start timing of the buffer flush function differs according to the value set in the IITV bit, as follows. (1) When IITV=0 The buffer flush operation is executed from the first frame after the pipe becomes valid. (2) When IITV > 0 The buffer flush operation is executed after the first successful transaction. Figure 3.21 provides an operation example of the controller buffer flush function. When a token is received outside of the specified interval period (before the interval frame), a written data packet or a zero-length packet is sent as an underrun error according to the data setup status SOF SOF Writing SOF Empty S Writing SOF Write end Buffer A Empty S Write end Tr ansfer -enabled Buffer flush generated Empty S Writing Buffer B Write end Tran sfer- enabled status Figure 3.21 Buffer Flush Function Operation Example Figure 3.22 shows an example of an interval error generated in the controller. There are 5 types of interval errors, as listed below. Timing 1 in the figure shows when the interval error occurs and how the buffer flush function operates. When an interval error occurs during an IN transfer, the buffer flush function goes into operation; during an OUT transfer, the NRDY interrupt is generated. Use the OVRN bit to determine whether an error is an NRDY interrupt, such as a receive packet error, or an overrun error. Responses to the tokens in the shaded boxes are executed in accordance to the buffer memory status. (1) IN direction: (a) If buffer is in transfer-enabled status, data is transferred as a normal response (b) If buffer is in transfer-disabled status, zero-length packet is sent and underrun error occurs (2) OUT direction: (a) If buffer is in receive-enabled status, data is received as a normal response (b) If buffer is in receive-disabled status, data is not received and overrun error occurs SOF (1) Successful transfer (2) Damaged token (3) Packet insertion (4) Frame miss (1) (5) Frame miss (2) (6) Delayed token Token Token Token Token Token Token Token Token Token Token Token 1 Token Token Token Token 1 Token Token Token 1 1 Token Token Token Token 1 1 1 Token Token Token Interval when IITV=1 Token received according to interval Token received in frame outside of interval Figure 3.22 Interval Error Occurrence Example When "IITV=1" Rev1.01 Oct 17, 2008 page 152 of 183 R8A66597FP/DFP/BG 3.9.6 Isochronous Transfer Payload when Host Controller function is selected When transferring a split-transaction in the isochronous pipe, set the MXPS bit to 188 bytes or less. Split-transaction tranfers occur when a Full-Speed device that performs isochronous transfers is connected to the Hi-Speed hub connected to the controller. Figure 3.25 shows a connection example. Table 3.26 shows the relation between the connection type and the maximum MXPS bit settings for the isochronous pipe. USB Cable USB cable USB Host embedded in R8A66597 (Hi-Speed transmission) Hi-Speed Hub (Full-Speed tra nsmissio n) Full-Speed Peripheral device with Isochronous endpoint Figure 3.23 Connection Example of Split-Transaction Transfer Table 3.26 Relation between Connection Type and Maximum of MXPS bit Setting for Isochronous Pipe No. (1) (2) (3) (4) (5) Connection Type Transfer speed Transfer speed of between R8A66597 peripheral device Controller and HUB connected to Hub Hi-Speed Hi-Speed Full-Speed Full-Speed Full-Speed Hi-Speed No Hub Full-Speed Maximum value for MXPS bit setting 1024 bytes 188 bytes 1023 bytes 1024 bytes 1023 bytes 3.10 SOF Interpolation Function When using the Peripheral Controller function and a receive is unsuccessful in the 1ms (Full-Speed operation) or 125us (Hi-Speed operation) interval due to SOF packet damage or loss, the SOF is interpolated by the controller internally. The start condition of the SOF interpolation is "USBE=1", "SCKE=1" and SOF packet receive. The controller initializes the SOF interpolation function under the following conditions. (1) H/W reset (2) USB bus reset (3) Suspend detection The SOF interpolation operates according to the following specifications. (1) Frame interval (125 us or 1ms) is based on the results of the reset handshake protocol. (2) The interpolation function does not operate until the SOF packet is received. (3) After the first SOF packet is received, the internal clock counts 125us or 1ms at 48MHz, then interpolates. (4) Interpolation is performed in the previous receive intervals after the 2nd and later SOF packets are received. (5) Interpolation is not performed in the suspend state or during a USB bus reset receive. When the controller goes to the suspend state in Hi-Speed operation, interpolation continues after 3ms from the last packet. The SOF interpolation function runs in the following functions. (1) Frame number or micro-frame number update (2) SOFR interrupt timing, SOF lock (3) SOF pulse output (4) Isochronous transfer interval count When an SOF packet is lost during Full-Speed operation, the FRMNUM register FRNM bit is not updated. When a SOF packet is lost during Hi-Speed operation, the UFRMNUM register UFRNM bit is updated. However, when a "FRNM=000" SOF packet is lost, the FRNM bit is not updated. At this time, even if SOF packets other than the "FRNM=000" packet are received successfully, the FRNM bit is not updated. Rev1.01 Oct 17, 2008 page 153 of 183 R8A66597FP/DFP/BG 3.10.1 SOF Pulse Output When SOF output is enabled, the controller outputs the SOF pulse according to the SOF timing. SOF pulse output is valid when either the Host or Peripheral Controller Function is selected. When the value of the SOFCFG register OSFM bit is "01" (1ms SOF) or "10" (125s SOF), the pulse is output in the "L" active state from the SOF N pin. This is called the "SOF signal". For more details concerning the pulse timing, refer to Figure 3.24. When using the Peripheral Controller function, SOF packet receive or SOF output due to "SOF interpolation" are output at even intervals. 1m s(Full-Speed) / 125us(High-Speed) SO F packet USB Bus SYNC PID FRAME CRC5 SO F m inim un 640ns Figure 3.24 SOF Output Timing Rev1.01 Oct 17, 2008 page 154 of 183 R8A66597FP/DFP/BG 3.11 Pipe Schedule 3.11.1 Transaction Issuance Conditions When the Host Controller function is selected, the controller supplies the internal clock and transactions are issued in the following conditions after "UACT=1" is set. Table 3.27 Transaction Issuance Conditions Transaction DIR Setup Control transfer data stage, status stage, and bulk transfer Interrupt transfer IN OUT IN OUT Isochronous transfer PID BUF BUF BUF BUF Issuance Conditions IITV *2) Buffer status invalid invalid valid valid Receive area available Send data in buffer Receive area available Send data in buffer *3) *4) SUREQ Set "1" *1) *2) *3) *4) IN BUF valid OUT BUF valid Slanted lines indicate this condition does not affect issuing of token. "Valid" indicates transaction is issued only in transfer frame by interval counter in interrupt and isochronous transfers. "Invalid" indicates transfer is issued regardless of interval counter. Transaction is issued regardless of available receive area. The receive data will be corrupted if no receive area is available. Transaction is issued regardless of send data in buffer. A zero-length packet will be sent if the is no send data. 3.11.2 Transfer Schedule The following is a description of the scheduling method for transfers in a frames. The controller conducts transfers in the following order after the SOF is sent. When using two ports and the combination of Port0 and Port1 transfer speeds are the same as case (3) or (4) shown in Table 3.4, the scheduling is split between 2 lines. Each line is scheduled in the order of steps (1) to (3). When the combination of Port0 and Port1 transfer speeds match cases (1) or (2), the scheduling is performed in one line. (1) Periodic transfer execution The controller searches pipes in the following order until it finds a pipe enabled to issue an isochronous or interrupt transfer transaction: Pipe 1 Pipe 2 Pipe 6 Pipe 7 Pipe 8 Pipe 9. When it finds an enabled pipe, the transaction is issued. (2) Control transfer setup transaction The controller confirms the DCP. If it is setup transaction enabled, the setup packet is sent. (3) Bulk transfers, Data stage or status stage of the control transfer execution The controller searches the pipes in the order below. When it finds a pipe enabled for transaction in the bulk or control transfer data stage or the control transfer status stage, the transaction is executed. Search order: DCP Pipe 1 Pipe 2 Pipe 3 Pipe 4 Pipe 5 When the transaction is issued, the sequence goes on to the transaction in the next pipe whether the response from the peripheral is ACK or NAK. Also, if there is time in the frame to execute another transfer, step (3) is repeated. 3.11.3 USB Transmission Enable Setting the DVSTCTR register UACT bit to "1" starts the SOF or SOF send and enables the transaction issuance. Setting the UACT bit to "0" the controller stops the SOF or SOF send and put the USB bus in the suspend status. Rev1.01 Oct 17, 2008 page 155 of 183 R8A66597FP/DFP/BG When the UACT bit is switched from "1" to "0", transfer is stopped after the next SOF or SOF is sent. Rev1.01 Oct 17, 2008 page 156 of 183 R8A66597FP/DFP/BG 3.12 USB Connector Connection example Figure 3.25shows an example of the connection between the controller and USB connector when the Host Controller function is selected, and Figure 3.26 shows an example of when the Peripheral Controller function is selected. R8A66597 VBOUT0 OVCUR0A OVCUR0B DM0 DP0 VBUS supply power switch VBUS output e nable VBUS outp ut Over-current detection D+ and D- lines must be configured to support impedance control 1 2 3 4 Vbus DD+ GND USB connector VBOUT1 OVCUR1 VBUS output enable VBUS o utput Over-current detection DM1 DP1 D+ and D- lines must be configured to support impedance control 1 2 3 4 Vbus DD+ GND REFRIN 5.6K? AGND USB connector Figure 3.25 USB Connector Connection Example when Host Controller Function is Selected R8A66597 VBUS DM0 DP0 1 2 3 4 5.6k? Vbus DD+ GND REFRIN AGND USB connector D+ and D- lines must be configured to support impedance control Figure 3.26 USB Connector Connection Example when Peripheral Controller Function is Selected Rev1.01 Oct 17, 2008 page 157 of 183 R8A66597FP/DFP/BG 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Symbol VIF VCC AVCC VBUS VI(IO) VO(IO) Pd Tstg Item IO power supply voltage Power supply voltage (3.3V) Analog power supply voltage (3.3V) VBUS input voltage System interface input voltage System interface output voltage Power consumption Storage temperature Rated vlalue -0.3 ~ +4.0 -0.3 ~ +4.0 -0.3 ~ +4.0 -0.3 ~ +5.5 -0.3 ~ VIF+0.3, VCC+0.3 -0.3 ~ VIF+0.3, VCC+0.3 600 -55 ~ +150 Unit V V V V V V mW degrees Celcius 4.2 Recommended Operating Conditions Symbol VIF VCC AVCC AGND GND VI(IO) VI(VBUS) VO(IO) IO power supply voltage Item 1.8V supported 3.3V supported Power supply voltage (3.3V) Minimum 1.6 2.7 3.0 3.0 Rated value Average 1.8 3.3 3.3 3.3 0 0 0 0 0 -20 -40 +25 +25 VIF, VCC 5.25 VIF, VCC +85 +85 500 5 Maximum 2.0 3.6 3.6 3.6 Unit V V V V V V V V V degrees Celcius degrees Celcius ns ms Analog power supply voltage (3.3V) Analog power supply GND Power supply GND System interfaceinput voltage Input voltage (VBUS input only) System interface output voltage R8A66597FP (Standard items) Ambient operating R8A66597DFP temperatrure (Optional items with wide temperature range) Normal input Input rise, fall times Schmitt Trigger input Topr tr, tf Rev1.01 Oct 17, 2008 page 158 of 183 R8A66597FP/DFP/BG 4.3 Electrical Characteristics (ratings for VIF = 2.7~3.6V) Symbol VIH VIL VIH VIL VT+ VTVTH VOH VOL VOH VOL VOH VOL VOH VOL VT+ VTIIH IIL IOZH IOZL Rdv Icc(A) Item "H" input voltage "L" input voltage "H" input voltage "L" input voltage Threshold voltage in positive direction Threshold voltage in negative direction Hysteresis voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage Threshold voltage in positive direction Threshold voltage in negative direction "H" input current "L" input current "H" output current in off stauts "L" output current in off stauts Pull-down resistance Average supply current during HS operation Average supply current during FS/LS operation Note 1 Note 2 Measurement conditions VCC = 3.6V VCC = 3.0V VIF = 3.6V VIF = 2.7V Minimum 2.52 0 0.7VIF 0 1.4 Note 3 VIF = 3.3V 0.5 0.8 Xout Note 4 Note 5 Note 6 VCC = 3.0V VCC = 3.0V VIF = 2.7V VIF = 2.7V IOH = -50uA IOL = 50uA IOH = -2mA IOL = 2mA IOH = -4mA IOL = 4mA IOH = -2mA IOL = 2mA 2.6 0.4 VCC-0.4 0.4 VIF-0.4 0.4 VIF-0.4 0.4 1.4 VBUS VCC = 3.3V 0.5 VIF,VCC = 3.6V Note 7 VBUS Note 8 f(Xin) = 48MHz VIF, VCC, AVCC = 3.6V USB Port 1-0 = HS operations f(Xin) = 48MHz VIF, VCC, AVCC = 3.6V USB Port 1-0 = FS/LS operation USB suspend status (Host Controller function) VIF = 3.6V USB suspend status (Peripheral Controller function) VIF = 3.6V USB cable detached VIF = 3.6V VIF = 3.6V VO = GND 500 70 -10 uA k mA VI = VIF,VCC VI = GND VO = VIF 1.65 10 -10 10 V uA uA uA 2.4 Rated value Typical Maximum 3.6 0.9 3.6 0.3VIF 2.4 1.65 Unit V V V V V V V V V V V V V V V V Icc(A) Note 8 22 mA 0.15 mA Icc(S) Supply current in static mode Note 8 0.35 0.15 7 7 mA mA pF pF CIN COUT Pin capacitance (Input) Pin capacitance (Output / I/O) Note 1: Xin, OVCUR1, ID0, OVCUR0A, OVCUR0B input pins Note 2: MPBUS, A7-1, input pin and DEND0-1_N, SD7-0, D15-0 input/output pin Note 3: DACK0-1_N, RST_N, RD_N, WR0-1_N, CS_N input pin Note 4: VBOUT0-1, EXTLP0 output pins Note 5: DREQ0-1_N output pin, and DEND0-1_N, SD7-0, D15-0 input/output pin Note 6: INT_N,SOF_N output pin Note 7: DEND0-1_N, SD7-0, D15-0 input/output pins Note 8: Supply current is the total of VIF, VCC, and AVCC currents Rev1.01 Oct 17, 2008 page 159 of 183 R8A66597FP/DFP/BG 4.4 Electrical Characteristics (Ratings for VIF = 1.6 ~ 2.0V) Symbol VIH VIL VIH VIL VT+ VTVTH VOH VOL VOH VOL VOH VOL VOH VOL VT+ VTIIH IIL IOZH IOZL Rdv Icc(A) Item "H" input voltage "L" input voltage "H" input voltage "L" input voltage Threshold voltage in positive direction Threshold voltage in negative direction Hysteresis voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage Threshold voltage in positive direction Threshold voltage in negative direction "H" input current "L" input current "H" output current in off stauts "L" output current in off stauts Pull-down resistance Average supply current during HS operation Average supply current during FS/LS operations Note 1 Note 2 Measurement conditions VCC = 3.6V VCC = 3.0V VIF = 2.0V VIF = 1.6V Minimum 2.52 0 0.7VIF 0 0.7 Note 3 VIF = 1.8V 0.2 0.5 Xout Note 4 Note 5 Note 6 VCC = 3.0V VCC = 3.0V VIF = 1.6V VIF = 1.6V IOH = -50uA IOL = 50uA IOH = -2mA IOL = 2mA IOH = -4mA IOL = 4mA IOH = -2mA IOL = 2mA 2.6 0.4 VCC-0.4 0.4 VIF-0.4 0.4 VIF-0.4 0.4 1.4 VBUS VCC = 3.3V 0.5 VIF = 2.0V VCC = 3.6V Note 7 VBUS Note 8 f(Xin) = 48MHz VIF=2.0V, VCC, AVCC = 3.6V USB Port 1-0 = HS operations f(Xin) = 48MHz VIF=2.0V,VCC,AVCC = 3.6V USB Port 1-0 = FS/LS operations USB suspend status (Host Controller function) VIF = 2.0V USB suspend status (Peripheral Controller function) VIF = 2.0V USB cable detached status VIF = 2.0V VIF = 2.0V VO = GND 500 70 -10 uA k mA VI = VIF,VCC VI = GND VO = VIF 1.65 10 -10 10 V uA uA uA 2.4 Rated value Typical Maximum 3.6 0.9 3.6 0.3VIF 1.4 0.8 Unit V V V V V V V V V V V V V V V V Icc(A) Note 8 20 mA 0.15 mA Icc(S) Supply current in static mode Note 8 0.35 0.15 7 7 mA mA pF pF Pin capacitance (Input) Pin capacitance COUT (Output / I/O) Note 1: Xin,OVCUR1, ID0, OVCUR0A, and OVCUR0B input pins Note 2: MPBUS, A7-1, input pin, and DEND0-1_N, SD7-0, D15-0 input/output pins Note 3: DACK0-1_N, RST_N, RD_N, WR0-1_N, CS_N input pins Note 4: VBOUT0-1, EXTLP0 output pin Note 5: DREQ0-1_N output pin, and DEND0-1_N, SD7-0, D15-0 input/output pin Note 6: INT_N,SOF_N output pin Note 7: DEND0-1_N, SD7-0, D15-0 input/output pins Note 8: Supply current is the total of VIF, VCC, and AVCC currents CIN Rev1.01 Oct 17, 2008 page 160 of 183 R8A66597FP/DFP/BG 4.5 Measurement Circuit 4.5.1 Pins except USB buffer section VIF,VCC Input VIF,VCC RL=1k SW1 D15-0, SD7-0, DEND0_N, SW2 DEND1_N RL=1k Other output CL GND Item tdis(CTRL(LZ)) tdis(CTRL(HZ)) ta(CTRL(ZL)) ta(CTRL(ZH)) SW1 Closed Open Closed Open SW2 Open Closed Open Closed P.G. 50 Elements to be measured CL (1) Input pulse level: 0-3.3V 0-1.8V Input pulse rise/fall time: tr, tf = 3ns Input timing standard voltage: VIF/2, VCC/2 Output timing judge voltage: VIF/2, VCC/2 (The tdis(LZ) is judged by 10% of the output amplitude and the tdis (HZ) by 90% of the output amplitude.) (2) The electrostatic capacity CL includes the stray capacitance of the wire connection and the input capacitance of the probe. 4.5.2 USB buffer block (Peripheral Controller function , Full-Speed) (1) The tr and tf are judged by the transition time of the 10% amplitude point and 90% amplitude point respectively. VCC (2) The electrostatic capacity CL includes the stray capacitance of the wire connection and the input capacitance of the probe. D+ DP Elements to be measured DM RL=15k DRL=15k CL CL GND 4.5.3 USB buffer block (Hi-Speed) (1) The tr and tf are judged by the transition time of the 10% amplitude point and 90% amplitude point respectively (2) The electrostatic capacity CL includes the stray capacitance of the wire connection and the input capacitance of the probe. D+ DP VCC Elements to bemeasured DM RL=45 DRL=45 CL CL GND Rev1.01 Oct 17, 2008 page 161 of 183 R8A66597FP/DFP/BG 4.6 Electrical Characteristics (D+/D-) 4.6.1 DC characteristics Item Reference resistance FS driver output impedance D+, D- pull-up resistance (Peripheral Controller function) Measurement conditions HS operation FS operation Idle status Transmitting and receiving status Minimum 5.544 40.5 28 0.9 1.425 Rated value Typical 5.6 45 36 Maximum 5.656 49.5 44 1.575 3.09 24.80 Unit k k k k V V V V Symbol RREF Ro Rpu Rpd VIH VIL VDI VCM D+, D- Pull-down resistance 14.25 (Host Controller function) Input characteristics for Full-Speed/Low-Speed operation "H" input voltage 2.0 "L" input voltage Differential input sensitivity (D+) - (D-) 0.2 Differential common mode range 0.8 0.8 2.5 Output characteristics for Full-Speed/Low-Speed operations RL of 1.5K to 3.6V VCC = 3.0V VOH "H" output voltage RL of 15K to GND 2.8 3.6 V VOL "L" output voltage 0.3 V VSE VORS VHSSQ VHSCM VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK Single-ended receiver threshold 0.8 voltage Output signal crossover voltage 1.3 Input characteristics for Hi-Speed operations Squelch detection threshold 100 voltage (differential) Common mode voltage range -50 Output characteristics for Hi-Speed operations Idle status -10.0 "H" output voltage 360 "L" output voltage -10.0 Chirp-J output voltage 700 (differential) Chirp-K output voltage -900 (differential) 2.0 2.0 150 500 10 440 10 1100 -500 V V mV mV mV mV mV mV mV Rev1.01 Oct 17, 2008 page 162 of 183 R8A66597FP/DFP/BG 4.6.2 Symbo l Tr Tf TRFM AC characteristics (Full-Speed) Item Rise transition time Fall transition time Rise/Fall time matching Measurement conditions 10%90% of the data signal amplitude 90%10% of the data signal amplitude Tr/Tf CL=50pF CL=50pF Minimum 4 4 90 Rated value Typical Maximum 20 20 111.11 Unit ns ns % 4.6.3 AC characteristics (Low-Speed) Item Rise transition time Fall transition time Rise/Fall time matching Measurement conditions 10%90% of the data signal amplitude 90%10% of the data signal amplitude Tr/Tf Minimum 75 75 80 Rated value Typical Maximum 300 300 125 Unit ns ns % Symbol Tr Tf TRFM Rev1.01 Oct 17, 2008 page 163 of 183 R8A66597FP/DFP/BG 4.7 Power Sequence, Reset Timming 4.7.1 Power Sequence VCC 3.0V 0.3V min.300s RST_N min.0ns min.500ns CS_N, WR0_N, WR1_N Note: Simultaneous Power-on and Power-off is recommended for VCC and AVCC. VIF Power-on timing is recommended to be simultaneous with VCC and AVCC, or to be earlier than VCC and AVCC. The VIF Power-off timing is recommended to be simultaneous with VCC and AVCC, or to be later than VCC and AVCC. Reset with RST_N is a must. If this sequence can't keep, normal operating is not guaranteed that even with conduct the operation of Reset timing of the chapter 4.7.2. 4.7.2 Reset timing of VCC=On status min.100ns RST_N min.500ns CS_N, WR0_N, WR1_N Rev1.01 Oct 17, 2008 page 164 of 183 R8A66597FP/DFP/BG 4.8 Switching Characteristic (VIF = 2.7~3.6V, or 1.6~2.0V) Measurement conditions,etc. Rated value Maximum Minimum Symbol Item Unit ta (A) tv (A) ta (CTRL - D) tv (CTRL - D) ten (CTRL - D) tdis (CTRL - D) ta (CTRL - DV) tv (CTRL - DV) ta (CTRL - DendV) Address access time Time that data is valid after address Time that data can be accessed after control Time that data is valid after control Time that data output is enabled after control Time that data output is disabled after control Time that data can be accessed after control when split bus (DMA Interface) Obus=0 Time that data can is valid after control when split bus (DMA Interface) Obus=0 Time that DEND output can be accessed after control when split bus (DMA Interface) Obus=0 Time that DEND output is valid after control when CPU bus and split bus (DMA Interface) Obus=0 Time that DEND output can be accessed after control when split bus (DMA Interface) Obus=1 Time that DEND output is valid after control when CPU bus and split bus (DMA Interface) Obus=1 Time that DEND output is enabled after control when CPU bus and split bus (DMA Interface) Obus=1 Time that DEND output is disabled after control when CPU bus and split bus (DMA Interface) Obus=1 Time that DREQ is disabled after control Time that DREQ is disabled after writing in DEND input is completed and control is completed Time that DREQ is enabled after control DREQ output "H" pulse width INT output negated delay time INT output "H" pulse width CL=50pF CL=10pF CL=50pF CL=10pF 2 2 CL=50pF CL=30pF CL=10pF CL=30pF 2 2 30 ns ns 30 ns ns ns 30 30 ns ns ns 30 ns tv (CTRL - DendV) CL=10pF 2 ns ta (CTRL - Dend) CL=30pF 30 ns tv (CTRL - Dend) CL=10pF 2 ns ten (CTRL - Dend) 2 ns tdis (CTRL-Dend) tdis (CTRL - Dreq) tdis (CTRLH -Dreq) ten (CTRL - Dreq) twh (Dreq) td (CTRL - INT) twh (INT) CL=30pF 30 30 30 20 20 70 50 250 650 0 ns ns ns ns ns ns ns ns Data access after DREQ begins to be asserted when split bus (DMA Interface) td (DREQ - DV) Obus=0 DEND output determination time after td (Dreq - DendV) starting DREQ assert, when Split bus (DMA Interface) Obus=0 or CPU BUS1, 2 Time that DREQ is disabled after end of tdis (PCTRLH - Dreq) previous control Key: ta: Access time, tv: Valid time, ten: Output enabled time, tdis: Output disabled time, (A): Address, (D): Data, (Dend): DiEND_N, (Dreq): DiREQ_N, (CTRL): Control, (V): Obus=0 0 70 ns ns Rev1.01 Oct 17, 2008 page 165 of 183 Reference Number Typical 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R8A66597FP/DFP/BG 4.9 Required Timing Conditions (VIF = 2.7~3.6V, or 1.6~2.0V) Measurement conditions, etc. Rated value Maximum Minimum Symbol Item Unit tsuw (A) tsur (A) tsu (A - ALE) thw (A) thr (A) th (A - ALE) tw (ALE) tdwr (ALE - CTRL) trec (ALE) tw (CTRL) trec (CTRL) Address write setup time Address read setup time Address setup time when using multiplex bus Address write hold time Address read hold time Address setup hold time when using multiplex bus ALE pulse width when using multiplex bus Write/Read delay time when using multiplex bus ALE recovery time when using multiplex bus Control pulse width (write) Control recovery time (FIFO) When using DMA interface cycle steal Other than above mentioned CL=50pF 10 0 10 0 10 0 10 7 0 30 30 12 12 30 10 0 10 0 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns trecr (CTRL) twr (CTRL) tsu (D) th (D) tsu (Dend) th (Dend) Control recovery time (REG) Control pulse width (read) Data setup time Data hold time DEND input setup time DEND input hold time FIFO/register access cycle time FIFO access cycle time only when DMA interface DACKi_N is used Control pulse width when using burst transfers 8/16-bit FIFO access (Separate bus) (Other than cases corresponding to 47-2) 8/16-bit FIFO access (Multiplex bus) 8-bit FIFO access tw (cycle1) 47-1 84 30 ns ns 47-2 tw (cycle2) 16-bit FIFO access When using split bus and Obus=0 When using split bus and Obus=1 (see Note) When using DMA transfers with CPU bus 50 ns 12 30 30 12 10 0 100 500 ns ns ns ns ns ns ns ns 49 50 51 52 53 48 tw (CTRL_B) trec (CTRL_B) tsud (A) thd (A) tw (RST) tst (RST) Rev1.01 Oct 17, 2008 Control recovery time for burst transfers DMA address write setup time DMA address write hold time Reset pulse width time Control starts width time after reset page 166 of 183 Reference number Typical 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 R8A66597FP/DFP/BG Key tsuw: Write setup time, tsur: Read setup time, tsu: setup time thw: Write hold time, thr: Read hold time, th: hold time, tw: Pulse width, twr: Read pulse width tdwr: Read/Write delay time, trec: Recovery time, trecr: Register recovery time tsud: DMA setup time, thd: DMA hold time, tst: start time (A): Address, (D): Data, (CTRL): Control, (CTRL_B): Burst control, (ALE): ALE Rev1.01 Oct 17, 2008 page 167 of 183 R8A66597FP/DFP/BG 4.10 Timing Diagrams 4.10.1 Index for register access timing diagram Bus Specifications Separate bus Separate bus Multiplex bus Multiplex bus Access CPU CPU CPU CPU R/W WRITE READ WRITE READ Index 4.11.1.1 4.11.1.2 4.11.2.1 4.11.2.2 Note CPU bus 0 CPU bus 0 CPU bus 0 CPU bus 0 4.10.2 Index for FIFO port access timing DFORM OBUS Bit Set Bit Set R/W Note Index Value Value CPU CPU bus 0 Separate bus Write CPU CPU bus 0 Separate bus Read 4.11.1.2 CPU CPU bus 0 Multiplex bus Write 4.11.2.1 CPU CPU bus 0 Multiplex bus Read 4.11.2.2 DMA CPU bus 2 Acknowledgement + RD/WR 010 Write Cycle steal transfer 4.11.3.1 *1 *1 DMA CPU bus 2 Acknowledgement + RD/WR 010 Read Cycle steal transfer 4.11.3.2 DMA CPU bus 1 Separate bus 000 Write Cycle steal transfer 4.11.3.3 DMA CPU bus 1 Separate bus 000 Read Cycle steal transfer 4.11.3.4 DMA SPLIT bus 2 Acknowledgement only 100 1 Write Cycle steal transfer 4.11.3.5 *1 Acknowledgement only DMA SPLIT bus 2 100 1 Read Cycle steal transfer 4.11.3.6 *1 Acknowledgement only DMA SPLIT bus 2 100 0 Write Cycle steal transfer 4.11.3.5 *1 Acknowledgement only DMA SPLIT bus 2 100 0 Read Cycle steal transfer 4.11.3.7 *1 Acknowledgement only DMA CPU bus 3 011 Write Cycle steal transfer 4.11.3.8 *1 Acknowledgement only DMA CPU bus 3 011 Read Cycle steal transfer 4.11.3.9 *1 DMA CPU bus 1 Multiplex bus 000 Write Cycle steal transfer 4.11.4.1 DMA CPU bus 1 Multiplex bus 000 Read Cycle steal transfer 4.11.4.2 DMA CPU bus 2 Acknowledgement + RD/WR 010 Write Burst transfer 4.11.5.1 *1 DMA CPU bus 2 Acknowledgement + RD/WR 010 Read Burst transfer 4.11.5.2 *1 DMA CPU bus 1 Separate bus 000 Write Burst transfer 4.11.5.3 DMA CPU bus 1 Separate bus 000 Read Burst transfer 4.11.5.4 Acknowledgement only DMA SPLIT bus 2 100 1 Write Burst transfer 4.11.5.5 *1 Acknowledgement only DMA SPLIT bus 2 100 1 Read Burst transfer 4.11.5.6 *1 Acknowledgement only DMA SPLIT bus 2 100 1 Write Burst transfer 4.11.5.5 *1 Acknowledgement only DMA SPLIT bus 2 100 1 Read Burst transfer 4.11.5.6*1 Acknowledgement only DMA SPLIT bus 2 100 0 Write Burst transfer 4.11.5.5 *1 Acknowledgement only DMA SPLIT bus 2 100 0 Read Burst transfer 4.11.5.7 *1 Acknowledgement only DMA CPU bus 3 011 Write Burst transfer 4.11.5.8 *1 Acknowledgement only DMA CPU bus 3 011 Read Burst transfer 4.11.5.9 *1 DMA CPU bus 1 Multiplex bus 000 Write Burst transfer 4.11.6.1 DMA CPU bus 1 Multiplex bus 000 Read Burst transfer 4.11.6.2 Note: *1) Because the address signal is not used, the timing will be the same for the separate bus and multiplex bus. The reading and writing timing are carried out using a control signal. If the control signal is configured from a combination of multiple signals, the rating from the falling edge will be valid starting from when the active delay signal changes. The ratings from the rising edge will be valid starting from the change in signals that become inactive more quickly. Access Bus I/F Specifications I/F Specifications When Operating Rev1.01 Oct 17, 2008 page 168 of 183 R8A66597FP/DFP/BG 4.11 Timing Diagram 4.11.1 CPU access timing (when a separate bus is set) 4.11.1.1 CPU access write timing (when a separate bus is set) 30 33 tsuw(A) A6-A1 thw(A) Address determination CS_N Note 1-3 47-1 tw(cycle1) 39 tw(CTRL) WR1_N, WR0_N trec(CTRL), 40 trecr(CTRL) 41 Note1-1 43 44 tsu(D) D15-D0 th(D) Data determination 4.11.1.2 CPU access read timing (when a separate bus is set) 1 ta(A) 31 tsur(A) 34 thr(A) A6-A1 Address determination CS_N Note 1-3 42 47-1 tw(cycle1) 40 41 twr(CTRL) RD_N Note 1-2 5 trec(CTRL), trecr(CTRL) 4 tv(A) 2 6 ta(CTRL-D) ten(CTRL-D) 3 tv(CTRL-D) tdis(CTRL-D) D15-D0 Data determination Note 1-1: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N. Note 1-2: The control signal, when reading data, is a combination of CS_N and RD_N. Note 1-3: RD_N, WR0_N, and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to fall when RD_N or WR0_N, and WR1_N are rising. In the above instances, an interval of at least 10ns must be left open. Rev1.01 Oct 17, 2008 page 169 of 183 R8A66597FP/DFP/BG 4.11.2 CPU access timing (when a multiplex bus is set) 4.11.2.1 CPU access write timing (when a multiplex bus is set) 47-1 tw (cycle1) 32 tsu (A - ALE) 35 th (A - ALE) 43 44 tsu (D) th (D) Address de termi nati on AD6-AD1 / D15-D0 36 A ddress de termi nation Data determination 38 tw (ALE) trec (ALE) ALE CS_N Note 2-3 37 tdwr (ALE - CTRL) 39 tw (CTRL) WR1_N, WR0_N Note 2-1 4.11.2.2 CPU access read timing (when a multiplex bus is set) 47-1 tw (cycle1) tdis (CTRL - D) tv (CTRL - D) 4 Address determination 32 tsu (A - ALE) Address determination th (A - ALE) 35 6 AD6-AD1 / D15-D0 36 Data determination ten (CTRL - D) 5 ta (CTRL - D) 3 trec (ALE) 38 tw (ALE) ALE CS_N Note 2-3 37 tdwr (ALE - CTRL) twr (CTRL) 42 RD_N Note 2-2 Note 2-1: The control signal when writing data is a combination of CS_N, WR1_N, and WR0_N. Note 2-2: The control signal when reading data is a combination of CS_N and RD_N. Note 2-3: RD_N, WR0_N, and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to fall when RD_N or WR0_N, and WR1_N are rising. In the above instances, an interval of at least 10ns must be left open. Rev1.01 Oct 17, 2008 page 170 of 183 R8A66597FP/DFP/BG 4.11.3 DMA access timing (when a cycle steal transfer, separate bus are set) 4.11.3.1 DMA cycle steal transfer write timing (CPU bus address is not used: DFORM=010) 25 17 20 tdis (PCTRLH - Dreq) tdis (CTRL - Dreq) DREQi_N (i=0,1) Note 3-1 twh (Dreq) 19 Note 3-10 DACKi_N (i=0,1) Note 3-8 tw (CTRL) WR1_N, WR0_N Note 3-2 43 39 ten (CTRL - Dreq) 40 trec (CTRL ) 44 tsu (D) D15-D0 th (D) Data determination tsu (Dend) 45 th (Dend) 46 DENDi_N (i=0,1) DENDi_N determintaion 4.11.3.2 DMACycle steal transfer read timing (CPU bus address not used: DFORM=010) 17 tdis (CTRL - Dreq) 20 twh (Dreq) DREQi_N (i=0,1) Note 3-1 19 ten (CTRL - Dreq) DACKi_N (i=0,1) Note 3-8 twr (CTRL) RD_N Note 3-3 5 ta (CTRL - D) 3 42 40 trec (CTRL ) tv (CTRL - D) 4 tdis (CTRL - D) 6 ten (CTRL - D) D15-D0 ta (CTRL - DendV) 11 Data determination tv (CTRL - DendV) 12 DENDi_N (i=0,1) Note 3-9 DENDi_N determination Rev1.01 Oct 17, 2008 page 171 of 183 R8A66597FP/DFP/BG 4.11.3.3 DMA Cycle steal transfer Write timing (CPU Separate bus setting:DFORM=000) 17 tdis (CTRL - Dreq) twh (Dreq) 20 ten (CTRL - Dreq) 19 DREQi_N (i=0,1) Note 3-1 25 tdis (PCTRLH - Dreq) tsud (A) 50 Note 3-10 thd (A) 51 A6-A1 CS_N Note 3-7 Address determination tw (CTRL) 39 WR0_N, WR1_N Note 3-5 tsu (D) 43 D15-D0 45 40 trec (CTRL ) th (D) 44 Data determination tsu (DEND) th (DEND) 46 DENDi _N (i=0,1) DENDi_N determination 4.11.3.4 DMA Cycle steal transfer read timing (CPU separate bus setting: DFORM=000) 17 tdis (CTRL - Dreq) twh (Dreq) 20 19 ten (CTRL - Dreq) DREQi_N (i=0,1) Note 3-1 31 ta (A) 1 tsur (A) A6-A1 CS_N Note 3-7 twr (CTRL) RD_N Note 3-6 5 ten (CTRL - D) ta (CTRL - D) 3 34 thr (A) Address determination 42 40 trec (CTRL ) 2 6 tdis (CTRL - D) tv (A) 4 tv (CTRL - D) D15-D0 ta (CTRL - DendV) 11 Data determination tv (CTRL - DendV) 12 DENDi _N (i=0,1) Note 3-9 DENDi_N detemination Rev1.01 Oct 17, 2008 page 172 of 183 R8A66597FP/DFP/BG 4.11.3.5 DMA Cycle steal transfer write timing (SPLIT bus: DFORM=100, OBUS=1/0) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) Note 3-1 twh (Dreq) 20 19 ten (CTRL - Dreq) 40 trec (CTRL ) tw (CTRL) 39 DACKi_N (i=0,1) 43 tsu (D) th (D) 44 SD7-SD0 45 Data determination tsu (Dend) th (Dend) 46 DENDi_N (i=0, 1) DENDi determination 4.11.3.6 DMA Cycle steal transfer read timing (SPLIT bus: DFORM=100, OBUS=1) 17 tdis (CTRL - Dreq) twh (Dreq) 20 DREQi_N (i=0, 1) Note 3-1 twr (CTRL) DACKi_N (i=0,1) 5 19 ten (CTRL - Dreq) 42 40 trec (CTRL ) ta (CTRL - D) 3 tv (CTRL - D) 4 6 ten (CTRL - D) SD7-SD0 15 tdis (CTRL - D) Data determination ta (CTRL - Dend) 13 tv (CTRL - Dend) 14 16 ten (CTRL - Dend) DENDi_N (i=0, 1) DENDi_N determination tdis (CTRL - Dend) Rev1.01 Oct 17, 2008 page 173 of 183 R8A66597FP/DFP/BG 4.11.3.7 DMA Cycle steal transfer read timing (SPLIT bus: DFORM=100, OBUS=0) DMA transfer begins 17 20 tdis (CTRL - Dreq) twh (Dreq) DREQi_N (i=0, 1) Note 3-1 twr (CTRL) DACKi_N (i=0, 1) 23 42 19 ten (CTRL - Dreq) 40 trec (CTRL ) td (DREQ - DV) ta (CTRL - DV) 9 tv (CTRL - DV) 10 SD7-SD0 Note 3-9 11 24 td (DREQ - DendV) ta (CTRL - DendV) DENDi_N (i=0, 1) Note 3-9 Data determination tv (CTRL - DendV) 12 DENDi_N determination 4.11.3.8 DMA Cycle steal transfer write timing (CPU BUS address not used: DFORM=011) 17 20 tdis (CTRL - Dreq) DREQi_N (i=0,1) twh (Dreq) Note 3-1 19 ten (CTRL - Dreq) 40 39 tw (CTRL) DACKi_N (i=0,1) Note 3-8 trec (CTRL) 43 44 tsu (D) D15-D0 th (D) Data determination tsu (Dend) 45 th (Dend) 46 DENDi_N (i=0,1) DENDi determination Rev1.01 Oct 17, 2008 page 174 of 183 R8A66597FP/DFP/BG 4.11.3.9 DMA Cycle steal transfer read timing (CPU BUS address not used: DFORM=011) 17 tdis (CTRL - Dreq) 20 twh (Dreq) DREQi_N (i=0,1) Note 3-1 twr (CTRL) 42 DACKi_N (i=0,1) Note 3-8 5 ta (CTRL - D) 3 19 ten (CTRL - Dreq) 40 trec (CTRL) tv (CTRL - D) 4 6 ten (CTRL - D) D15-D0 tdis (CTRL - D) Data determination ta (CTRL - DendV) 11 tv (CTRL - DendV) 12 DENDi_N (i=0,1) Note 3-9 DENDi_N determination Note 3-1: The control signal is the inactive condition for DREQi_N (i=0, 1). When the next DMA transfer exists, the delay ratings for twh (Dreq) and ten (CTRL-Dreq) will be valid until DREQi_N becomes active is twh (Dreq). Note 3-2: The control signal when writing data is a combination of DACKi_N, WR1_N, and WR0_N. Note 3-3: The control signal when reading data is a combination of DACKi_N and RD_N. Note 3-4: The control signal when writing data is a combination of DACK0 and DSTRB0_N. Note 3-5: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 3-6: The control signal when reading data is a combination of CS_N and RD_N. Note 3-7: RD_N, WR0_N and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to fall when RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open. Note 3-8: RD_N, WR0_N and WR1_N should not be timed to fall when DACKi_N is rising (or falling). Similarly, DACK should not be timed to fall (or rise) when RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open. Note 3-9: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined time is "(24)td(DREQ-DendV)". Note 3-10: The time required ultil DREQi_N (i=0,1) becomes active is valid, when the next DMA transfer exists, and when tdis (CTRL-Dreq) or tdis (PCTRLH - Dreq) has slow ratings. Rev1.01 Oct 17, 2008 page 175 of 183 R8A66597FP/DFP/BG 4.11.4 DMA access timing (Cycle steal transfer, when a multiplex bus is set) 4.11.4.1 DMA cycle steal transfer write timing (CPU multiplex bus settings: DFORM=000) Note 4-5 25 tdis (PCTRLH - Dreq) 17 twh (Dreq) 20 DREQi_N (i=0,1) 32 tdis (CTRL - Dreq) ten (CTRL - Dreq) 19 tsu (D) 43 35 tsu (A - ALE) th (A - ALE) Address determination th (D) 44 Address determination AD6-AD1 / D15-D0 Data determination 38 tw (ALE) 36 trec (ALE) ALE CS_N Note 4-3 WR1_N, WR0_N Note 4-1 DENDi_N (i=0,1) 37 tdwr (ALE - CTRL) tw (CTRL) 39 45 tsu (DEND) th (DEND) 46 DENDi_N determination 4.11.4.2 DMA Cycle steal transfer read timing (CPU Multiplex bus setting:DFORM=000) 17 tdis (CTRL - Dreq) twh (Dreq) 20 19 ten (CTRL - Dreq) DREQi_N (i=0,1) 32 tsu (A - ALE) th (A - ALE) Address determination 35 tdis (CTRL - D) 6 tv (CTRL - D) 4 A6-A1 / D15-A0 36 Data determination ten (CTRL - D) 5 ta (CTRL - D) 3 Address determination tw (ALE) ALE CS_N Note 4-3 37 twr (CTRL) 42 tdwr (ALE - CTRL) trec (ALE) 38 RD_N Note 4-2 DENDi _N (i=0,1) Note 4-4 ta (CTRL - DendV) 11 12 tv (CTRL - DendV) DENDi_N determination Note 4-1: The control signal when writing data is a combination of CS_N, WR0_N, and WR1_N. Note 4-2: The control signal when reading data is a combination of CS_N and RD_N. Note 4-3: RD_N, WR0_N and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to fall when RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open. Note 4-4 : When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)". Note 4-5: The time required until DREQi_N (i=0,1) becomes active is valid, when the next DMA transfer exists, and when tdis (CTRL-Dreq) or tdis (PCTRLH - Dreq) has slow ratings. Rev1.01 Oct 17, 2008 page 176 of 183 R8A66597FP/DFP/BG 4.11.5 DMA access timing (burst transfer and separate bus are set) 4.11.5.1 DMA burst transfer write timing (CPU BUS address not used: DFORM=010) 25 tdis (PCTRLH - Dreq) Note 5-9 tdis (CTRL - Dreq) 17 DREQi_N (i=0,1) DACKi_N (i=0,1) Note 5-8 48 tdis (CTRLH - Dreq) 18 tw (cycle1) 471 WR1_N, WR0_N Note 5-1 tw (CTRL_B) trec (CTRL_B) 49 43 tsu (D) th (D) 44 D15-D0 D0 D1 D2 Dn 45 tsu (Dend) th (Dend) 46 DENDi_N (i=0,1) 4.11.5.2 DMA burst transfer read timing (CPU BUS address not used: DFORM=010) 17 tdis (CTRL - Dreq) DREQi_N (i=0,1) DACKi_N (i=0,1) Note 5-8 48 tw (cycle1) 47-1 tw (CTRL_B) trec (CTRL_B) 49 RD_N Note 5-2 3 ta (CTRL - D) tv (CTRL - D) 4 D15-D0 DENDi _N (i=0,1) Note 5-6 D0 D1 11 Dn-1 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) Rev1.01 Oct 17, 2008 page 177 of 183 R8A66597FP/DFP/BG 4.11.5.3 DMA Burst transfer write timing (Separate bus setting:DFORM=000) Note 5-9 25 tdis (PCTRLH - Dreq) tdis (CTRL - Dreq) 17 DREQi _N (i=0,1) 50 tdis (CTRLH - Dreq) 18 tsud (A) thd (A) 51 Address determination Address determination Address determination A6-1 CS_N Note 5-7 48 Address determination tw (cycle1) 47-1 tw (CTRL_B) trec (CTRL_B) 49 WR0_N, WR1_N Note 5-4 D15-D0 43 tsu (D) th (D) 44 D0 D1 D2 Dn 46 45 tsu (DEND) th (DEND) DENDi _N (i=0,1) 4.11.5.4 DMA burst transfer read timing (separate bus setting: DFORM=000) tdis (CTRL - Dreq) 17 DREQi_N (i=0,1) 31 tsur (A) thr (A) 34 Address determination Address determination Address determination A6-A1 CS_N Note 5-7 48 Address determination tw (cycle1) 47-1 tw (CTRL_B) trec (CTRL_B) 49 RD_N Note 5-5 3 ta (A) 1 ta (CTRL-D) tv (A) 2 tv (CTRL-D) 4 D15-D0 DENDi_N (i=0,1) Note 5-6 D0 D1 11 Dn-1 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) Rev1.01 Oct 17, 2008 page 178 of 183 R8A66597FP/DFP/BG 4.11.5.5 DMA burst transfer write timing (SPLIT bus: DFORM=100, OBUS=1/0) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH - Dreq) DREQi_N (i=0, 1) 48 tw (cycle2) 47-2 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0, 1) 43 tsu (D) th (D) 44 SD7-SD0 D0 D1 D2 Dn 46 45 tsu (Dend) th (Dend) DENDi_N (i=0, 1) 4.11.5.6 DMABurst transfer read timing (SPLIT bus:DFORM=100, OBUS=1) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) tw (cycle2) 47-2 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0, 1) 3 48 ta (CTRL - D) SD7-SD0 tv (CTRL - D) 4 D0 D1 13 Dn-1 ta (CTRL - Dend) Dn 14 tv (CTRL - DendV) DENDi_N (i=0, 1) Rev1.01 Oct 17, 2008 page 179 of 183 R8A66597FP/DFP/BG 4.11.5.7 DMA burst transfer read timing (SPLIT bus: DFORM=100, OBUS=0) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) 48 47-2 tw (cycle2) tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0, 1) 23 td (DREQ - DV) 9 ta (CTRL - DV) tv (CTRL - DV) 10 SD7-SD0 Note 5-6 DENDi_N (i=0, 1) Note 5-6 D0 24 td (DREQ - DendV) D1 Dn-1 11 ta (CTRL - DendV) Dn 12 tv (CTRL - DendV) Rev1.01 Oct 17, 2008 page 180 of 183 R8A66597FP/DFP/BG 4.11.5.8 DMA burst transfer write timing (CPU BUS address not used: DFORM=011) 17 tdis (CTRL - Dreq) 18 tdis (CTRLH Dreq) DREQi_N (i=0,1) tw (cycle2) 47-2 48 DACKi_N (i=0,1) tw (CTRL_B) trec (CTRL_B) 49 43 tsu (D) th (D) 44 D15-D0 D0 D1 D2 Dn 45 tsu (Dend) th (Dend) 46 DENDi_N (i=0,1) 4.11.5.9 DMA burst transfer read timing (CPU BUS address not used: DFORM=011) 17 tdis (CTRL - Dreq) DREQi_N (i=0,1) 48 tw (cycle2) 47-2 tw (CTRL_B) trec (CTRL_B) 49 DACKi_N (i=0,1) 3 4 ta (CTRL - D) tv (CTRL - D) D15-D0 D0 D1 11 Dn-1 Dn 12 tv (CTRL - DendV) ta (CTRL - DendV) DENDi _N (i=0,1) Note 5-6 Note 5-1 : The control signal when writing data is a combination of DACKi_N(i=0, 1), WR0_N and WR1_N. Note 5-2 : The control signal when reading data is a combination of DACKi_N and RD_N. Note 5-3 : The control signal when writing data is a combination of DACK0 and DSTRB0_N. Note 5-4 : The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 5-5 : The control signal when reading data is a combination of CS_N and RD_N. Note 5-6 : When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined time is "(24)td(DREQ-DendV)". Note 5-7: RD_N, WR0_N and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to fall when RD_N, WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open. Note 5-8: RD_N, WR0_N and WR1_N should not be timed to fall when DACKi_N is rising (or falling). Similarly, DACKi_N should not be timed to fall (or rise) when RD_N, WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open. Note 5-9:The time required until DREQi_N (i=0,1) becomes active is valid, when the next DMA transfer exists, and when tdis (CTRL-Dreq) or tdis (PCTRLH - Dreq) has slow ratings. Rev1.01 Oct 17, 2008 page 181 of 183 R8A66597FP/DFP/BG 4.11.6 DMA access timing (burst transfer, when a multiplex bus is set) 4.11.6.1 DMA burst transfer write timing (CPU multiplex bus setting: DFORM=000) Note 6-5 25 tdis (PCTRLH - Dreq) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) tsu (A - ALE) AD6-AD1 / D15-D0 32 Address 18 tdis (CTRLH - Dreq) 35 43 tsu (D) th (D) 44 Address thw (A - ALE) D0 tw (cycle1) D1 Address Dn tw (ALE) ALE CS_N Note 6-3 48 36 47-1 tdwr (ALE_CTRL) 37 trec (CTRL_B) 49 46 45 tsu (DEND) tw (CTRL_B) WR0_N, WR1_N Note 6-1 DENDi_N (i=0, 1) th (DEND) 4.11.6.2 DMA burst transfer read timing (CPU multiplex bus setting: DFORM=000) 17 tdis (CTRL - Dreq) DREQi_N (i=0, 1) tsu (A - ALE) th (A - ALE) 35 AD6-AD1 / D15-D0 32 Address 3 ta (CTRL-D) tv (CTRL-D) 4 Address D0 tw (cycle1) Address D1 Dn tw (ALE) ALE CS_N Note 6-3 36 47-1 tdwr (ALE_CTRL) 37 trec (CTRL_B) 49 tw (CTRL_B) 48 RD_N Note 6-2 11 ta (CTRL - DendV) tv (CTRL - DendV) 12 DENDi_N (i=0, 1) Note 6-4 Note 6-1: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N. Note 6-2: The control signal when reading data is a combination of CS_N and RD_N. Note 6-3: RD_N, WR0_N and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to fall when RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open. Note 6-4 : When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)". Note 6-5:The time required until DREQi_N (i=0,1) becomes active is valid, when the next DMA transfer exists, and when tdis (CTRL-Dreq) or tdis (PCTRLH - Dreq) has slow ratings. Rev1.01 Oct 17, 2008 page 182 of 183 R8A66597FP/DFP/BG 4.12 Interrupt Timing 22 twh (INT) INT_N 21 td (CTRL - INT) CS_N, WR0_N, WR1_N Note 7-1 Note7-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active ("L") overlap period. The ratings from the rising edge are valid starting from the earliest change in the inactive signal. Rev1.01 Oct 17, 2008 page 183 of 183 Revision history R8A66597 Data Sheet Description Summary Rev. 1.00 1.01 Date May 30, 2008 Oct.17.2008 Page 7 41 42 44 45 159 160 164 Rev.1.00 issued Correct: VDD description of functions Correct:CFIFOSEL/REW bit H/W "R" "R/W(0)" Add:2.8.4 "When the software writes "1" to this bit, the controller again writes "0" to this bit." Correct:DxFIFOSEL/REW bit H/W "R" "R/W(0)" Correct:C/DxFIFOCTR/BCLR bit H/W "R" "R/W(0)" Add:Chapter 4.3, ICC(A),ICC(S) Add:Chapter 4.4, ICC(A),ICC(S) Correct:Chapter 4.7 Reset Timming Chapter 4.7 Power Sequence, Reset Timming Update:4.7.1 Power Sequence, update Note (1/1) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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